LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_unsigned.all;
entity mashup_sign Is
end mashup_sign;

architecture mashup of mashup_sign IS

signal clk_T_all        : std_logic;
signal r_reset_T_all        : std_logic;
signal r_ready_T_all        : std_logic;
signal r_towork_request_T_DMA   : std_logic;
signal r_comand_address_T_DMA   : std_logic_vector(0 to 15);
signal r_cs_DMA_RAM     : std_logic;
signal r_cs_CPU_RAM     : std_logic;
signal r_command_DMA_RAM    : std_logic_vector (0 to 1);
signal r_address_DMA_RAM    : std_logic_vector (0 to 15);
signal r_address_CPU_RAM    : std_logic_vector (0 to 15);
signal r_output_DMA_Test    : std_logic_vector (0 to 2);
signal r_data_RAM_DMA       : std_logic_vector (0 to 63);
signal r_data_CPU_RAM       : std_logic_vector (0 to 63);
signal r_data_DMA_RAM       : std_logic_vector (0 to 63);



component FSM_DMA_C is
port (                         -- r_ - register
    clk         :IN     std_logic; --
    r_ready         :IN std_logic; -- 0 ничё не меняется
    r_towork_request    :IN     std_logic; --
    r_reset         :IN     std_logic; --
    r_command_address   :IN std_logic_vector (0 to 15); --
    r_data_in       :IN std_logic_vector (0 to 63); --+
    r_cs            :OUT    std_logic; --+
    r_address_out       :OUT    std_logic_vector (0 to 15); --+
    r_data_out      :OUT    std_logic_vector (0 to 63); --+
    r_command       :OUT    std_logic_vector (0 to 1); --+ 01 read , 10 - write
    r_output        :OUT    std_logic_vector (0 to 2)); --+
end component;



component RAM is
port (
    r_reset             :in std_logic; --+
    r_ready             :in std_logic; --+
    clk             : in std_logic; --+
    r_CPU_cs            : in std_logic; --+
    r_CPU_data_in           : in std_logic_vector (0 to 63); --+
    r_CPU_address           : in std_logic_vector (0 to 15); --+
    r_DMA_cs            : in std_logic; --+
    r_DMA_data_in           : in std_logic_vector (0 to 63); --+
    r_DMA_command           : in std_logic_vector (0 to 1); --+
    r_DMA_address           : in std_logic_vector (0 to 15);--+
    r_DMA_data_out          : out std_logic_vector (0 to 63)); --+
end component;




component Tester is
Port (
    r_CPU_cs        :OUT    std_logic; --+
    r_CPU_RAM_data_in   :OUT    std_logic_vector (0 to 63); --+
    r_CPU_RAM_address   :OUT    std_logic_vector (0 to 15); --+
    r_output        :IN std_logic_vector (0 to 2); --+
    r_ready         :OUT    std_logic; -- 0 ничё не меняется
    r_request       :OUT    std_logic; --+
    clk         :OUT    std_logic; --+
    r_address_DMA_in        :OUT    std_logic_vector (0 to 15); --+
    r_reset         :OUT    std_logic); --+
END component;

begin
Inst_FSM_DMA_C : FSM_DMA_C PORT MAP (
        clk             => clk_T_all,
        r_ready         => r_ready_T_all,
        r_towork_request    => r_towork_request_T_DMA,
        r_reset         => r_reset_T_all,
        r_command_address   => r_comand_address_T_DMA,
        r_data_in       => r_data_RAM_DMA,
        r_cs            => r_cs_DMA_RAM,
        r_address_out       => r_address_DMA_RAM,
        r_data_out      => r_data_DMA_RAM,
        r_command       => r_command_DMA_RAM,
        r_output        => r_output_DMA_Test
        );

Inst_RAM : RAM PORT MAP (
        clk             => clk_T_all,
        r_reset         => r_reset_T_all,
        r_ready         => r_ready_T_all,
        r_CPU_cs        => r_cs_CPU_RAM,
        r_CPU_data_in       => r_data_CPU_RAM,
        r_CPU_address       => r_address_CPU_RAM,
        r_DMA_cs        => r_cs_DMA_RAM,
        r_DMA_data_in       => r_data_DMA_RAM,
        r_DMA_command       => r_command_DMA_RAM,
        r_DMA_address       => r_address_DMA_RAM,
        r_DMA_data_out      => r_data_RAM_DMA);

Inst_Tester : Tester PORT MAP (
        r_CPU_cs        => r_cs_CPU_RAM,
    r_CPU_RAM_data_in   => r_data_CPU_RAM,
    r_CPU_RAM_address   => r_address_CPU_RAM,
    r_output        => r_output_DMA_Test,
    r_ready         => r_ready_T_all,
    r_request       => r_towork_request_T_DMA,
    clk         => clk_T_all,
    r_address_DMA_in    => r_comand_address_T_DMA,
    r_reset         => r_reset_T_all
);
end mashup;