DNALock

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    16:55:43 10/12/2015
-- Design Name:
-- Module Name:    DNALock - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity DNALock is
    port(
    CLK_98MHz     : in  std_logic;
    readDNACmd    : in  std_logic;
    DNA_SerailIn  : in  std_logic;
    SR_Clear      : in  std_logic;
    areset        : in  std_logic;
    DNA_Shift     : out std_logic:='0';
    DNA_Read      : out std_logic:='0';
    DNA_CLK       : buffer std_logic;
    DNAVerify     : out std_logic:='0';
    DNAReady          : out std_logic:='0');
end DNALock;

architecture Behavioral of DNALock is

-- Defining medium signals for shift register
signal  SR_read: std_logic:= '0';
signal  SR_clk : std_logic:= '0';
signal   SR_Out: std_logic_vector(63 downto 0) := (others => '0');
signal   SR_DataReady:std_logic:= '0';

--DNA clock medium signal
signal   DNA_CLK_Temp: std_logic :='0';


--10MHz signal period
constant DNA_CLK_period : time := 100 ns;
--Device DNA
constant DeviceDNA :std_logic_vector(63 downto 0) :=X"FFFFFFFFFFFFFFFF";

signal  clkCounter: unsigned(7 downto 0):= "00000000";
signal  clkCounter2: unsigned(7 downto 0):= "00000000";
signal   SR_Readb :std_logic:= '1';
--Defining state machine states:
type controllerState is (zeroState,initState,readState,endReadState);
signal state : controllerState;

begin

    --Magic clock generator!
    DNA_CLK_Temp <= not DNA_CLK_Temp after DNA_CLK_period/2;


    SR_Readb <= '1';

    --This process make read and shift signals for DNA device
--  controller:process(DNA_CLK_Temp)
--
--      variable COUNT    :unsigned(7 downto 0) := "00000000";
--      variable readFlag :bit:='0';
--      variable busyFlag :bit:='0';
--
--  begin
--  if (DNA_CLK_Temp'event and DNA_CLK_Temp = '1') then
--      if readFlag = '1' then
--          DNA_Read  <= '0';
--          DNA_Shift <= '1';--after 20 ns;
--          readFlag :=  '0';
--      end if;
--
--      if readDNACmd = '1' and busyFlag = '0' then
--          busyFlag  := '1';
--          readFlag :=  '1';
--          DNA_Read  <= '1';
--          SR_read   <= '1';
--          SR_clk    <= DNA_CLK;
--      end if;
--
--      if busyFlag = '1' then
--          COUNT := COUNT + 1;
--      end if;
--
--      if COUNT = 66 then
--          busyFlag := '0';
--          DNA_Shift <= '0' after 20 ns;
--          SR_read <= '0';
--          SR_clk  <= '0';
--      end if;
--  end if;
--  end process Controller;
    --Implementing controller using FSM


    FSMStateController:process(DNA_CLK_Temp,areset)

    --variable clkCounter    :unsigned(7 downto 0) := "00000000";

    begin

    if (areset = '1') then
        state <= zeroState;
    elsif (DNA_CLK_Temp'event and DNA_CLK_Temp = '1') then
        case state is
            when zeroState =>
                if readDnaCmd = '1' then
                    state <= initState;
                end if;

            when initState =>
                state <= readState;

            when readState =>
                --clkCounter := clkCounter + 1;
                clkCounter <= clkCounter + X"01";
                if clkCounter = X"40" then
                    state <= endReadState;
                end if;

            when endReadState =>
                state <= zeroState;

        end case;
    end if;

    end process FSMStateController;


    FSMOutputController:process(state,readDnaCmd)

    variable clkCounter    :unsigned(7 downto 0) := "00000000";

    begin

        case state is
            when zeroState =>
                if readDnaCmd = '1' then
                    DNA_Read <= '1';
                    SR_read   <= '0';
                else
                    SR_read   <= '1';
                end if;
            when initState =>
                DNA_Read  <= '0';
                SR_read   <= '1';
                SR_clk    <= DNA_CLK_temp;
                DNA_Shift <= '1';

            when endReadState =>
                DNA_shift <= '0';
                SR_read   <= '0';
            when readState =>
                clkCounter := clkCounter + 1;
                --clkCounter2 <= clkCounter2 + X"01";
                SR_read   <= '0';
        end case;

    end process FSMOutputController;



    --Implementing a 64-bit shift register to read from DNA device
    shiftRegister:process(DNA_CLK_Temp)
    variable COUNT2:unsigned(7 downto 0):= "00000000";
    begin
    if (DNA_CLK_Temp'event and DNA_CLK_Temp = '1') then

        if SR_read = '1' then
            SR_Out(to_integer(COUNT2)) <=  DNA_SerailIn;
            COUNT2 := COUNT2 + 1;
        end if;

        if COUNT2 = 64 then
            SR_DataReady <= '1';
            COUNT2 := "00000000";
        end if;

    end if;
    end process shiftRegister;

    checkDNA:process(SR_DataReady)
    begin
    if (SR_DataReady = '1') then
        DNAReady <= '1';
        if DeviceDNA = SR_Out then
            DNAVerify <= '1';
        end if;
        DNAReady <= '0' after 500 ns;
    end if;
    end process checkDNA;

    DNA_CLK <= DNA_CLK_Temp;

end Behavioral;