// Top Test Bench

module tb;
  // Interface instantiation
  div_if #(32) div_intf();

  // DUT instantiation
  div #(.DATA_WIDTH(32)) div_inst (
    .clk(div_intf.clk),
    .rst_n(div_intf.rst_n),
    .dividend(div_intf.dividend),
    .divisor(div_intf.divisor),
    .signed_ope(div_intf.signed_ope),
    .start(div_intf.start),
    .flush(div_intf.flush),
    .quotient(div_intf.quotient),
    .remainder(div_intf.remainder),
    .ready(div_intf.ready)
  );

  // Clock generation
  initial begin
    div_intf.clk = 0;
    forever #5 div_intf.clk = ~div_intf.clk;
  end

  // Reset task
  task reset();
    div_intf.rst_n = 0;
    div_intf.start = 0;
    div_intf.flush = 0;
    @(posedge div_intf.clk);
    div_intf.rst_n = 1;
  endtask

  // Monitor task to print signals every clock cycle
  task monitor_signals();
    $display("Time: %0t | clk: %b | rst_n: %b | start: %b | ready: %b | flush: %b | signed_ope: %b", $time, div_intf.clk, div_intf.rst_n, div_intf.start, div_intf.ready, div_intf.flush, div_intf.signed_ope);
    $display("           | dividend: %0d | divisor: %0d | quotient: %0d | remainder: %0d", $signed(div_intf.dividend), $signed(div_intf.divisor), $signed(div_intf.quotient), $signed(div_intf.remainder));
  endtask

  // Run the environment and monitor signals
  initial begin
    div_env env = new(div_intf);

    // Apply reset
    reset();

    // Monitor and display signals during execution
    fork
      forever begin
        @(posedge div_intf.clk);
        monitor_signals();
      end
      env.run();  // Run the test environment
    join_none

    #100;
    $finish;
  end

  // Dump waveforms
  initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, tb);
  end
endmodule