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mayankherode_04

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Sep 12th, 2023
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  1. module matrix_multiplier (
  2.   input wire clk,
  3.   input wire rst,
  4.   input wire [31:0] matrix_A,
  5.   input wire [31:0] matrix_B,
  6.   output wire [31:0] matrix_C
  7. );
  8.  
  9. reg [15:0] temp_result [0:3][0:3];
  10. reg [15:0] matrix_C_ [0:3][0:3];
  11.  
  12. reg [2:0] i, j, k;
  13. reg multiply_done;
  14.  
  15. always @(posedge clk) begin
  16. if (rst) begin
  17. i <= 0;
  18. j <= 0;
  19. k <= 0;
  20. multiply_done <= 0;
  21. end
  22. else begin
  23. if (!multiply_done) begin
  24. if (k < 4) begin
  25. temp_result[i][j] <= temp_result[i][j] + matrix_A[i * 4 + k] * matrix_B[k * 4 + j];
  26. k <= k + 1;
  27. end
  28.  else if (j < 3) begin
  29. k <= 0;
  30. j <= j + 1;
  31. end
  32. else if (i < 3) begin
  33. k <= 0;
  34. j <= 0;
  35. i <= i + 1;
  36. end
  37. else begin
  38. multiply_done <= 1;
  39. end
  40. end
  41. else begin
  42. if (i < 3) begin
  43. j <= 0;
  44. i <= i + 1;
  45. end
  46. else begin
  47. i <= 0;
  48. multiply_done <= 0;
  49. end
  50. end
  51. end
  52. end
  53.  
  54. always @(posedge clk or posedge rst) begin
  55. if (rst) begin
  56. i = 0;
  57. j = 0;
  58. loop_rst: begin
  59. if (i < 4) begin
  60. if (j < 4) begin
  61. temp_result[i][j] <= 16'h0;
  62. matrix_C_[i][j] <= 16'h0;
  63. j = j + 1;
  64. end
  65. else begin
  66. j = 0;
  67. i = i + 1;
  68. end
  69. end
  70. else begin
  71. i = 0;
  72. end
  73. end
  74. end
  75. else if (multiply_done) begin
  76. i = 0;
  77. j = 0;
  78. loop_multiply_done: begin
  79. if (i < 4) begin
  80. if (j < 4) begin
  81. matrix_C_[i][j] <= temp_result[i][j];
  82. j = j + 1;
  83. end
  84. else begin
  85. j = 0;
  86. i = i + 1;
  87. end
  88. end
  89. else begin
  90. i = 0;
  91. end
  92. end
  93. end
  94. end
  95. endmodule
  96.  
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