AVR | (ATtiny24a) PWM

#define F_CPU 1000000UL
#include <avr/io.h>
#include <util/delay.h>

#define SW_DOWN (1<<PA0)
#define SW_DOWN_ON !(PINA & SW_DOWN)

#define SW_UP (1<<PA3)
#define SW_UP_ON !(PINA & SW_UP)

#define MAX 0xFF


//płynna zmiana częstotliwości PWM

int main(void)
{
    unsigned int PWM_val = 0;               // PWM main value

    DDRA &= ~(SW_DOWN | SW_UP);             // Switch input UP & DOWN
    PORTA |= (SW_DOWN | SW_UP);

    DDRA    |= ((1<<PA5) | (1<<PA6) | (1<<PA7));    // PWM output on PA6 (OC1A), PA7 (OC0B), PA5 (OC1B)
    DDRB    |= (1 << PB2);                          // PWM output on PB2 (OC0A)

    TCCR0A = (1 << COM0A1) | (1 << COM0B1) | (1 << WGM00);      // phase correct PWM mode (OCR0x outputs)
    TCCR1A = (1 << COM1B1) | (1 << COM1A1) | (1 << WGM10);      // phase correct PWM mode (OCR1x outputs)

    TCCR0B = (1 << CS01);               // clock source = CLK/8, start PWM, for OC0x
    TCCR1B = (1 << CS11);               // clocl source = CLK/8, start PWM, for OC1x

    while(1)
    {
        if (SW_UP_ON)
            {
            _delay_ms(30);

            if (PWM_val < (MAX*4))  PWM_val+=5;
            else PWM_val = MAX*4;
            }
        else if (SW_DOWN_ON)
            {
            _delay_ms(30);

            if (PWM_val > 0) PWM_val-=5;
            else PWM_val = 0;
            }

        if ( (PWM_val > 0) && (PWM_val < MAX) )
            {
                OCR0A = PWM_val;
            }
        else if ( (PWM_val > MAX) && (PWM_val < (MAX*2)) )
            {
                OCR0A = 0xFA;
                OCR0B = PWM_val - MAX;
            }
        else if ( (PWM_val > (MAX*2)) && (PWM_val < (MAX*3)) )
            {
                OCR0B = 0xFA;
                OCR1A = PWM_val - (MAX*2);
            }
        else if ( (PWM_val > (MAX*3)) && (PWM_val < (MAX*4)) )
            {
                OCR1A = 0xFA;
                OCR1B = PWM_val - (MAX*3);
            }

    }
}