[bits 64]

%define READ_PORT 0x1f0
%define ATA_DRIVE_HEAD_PORT 0x1f6
%define SECTOR_COUNT_PORT 0x1f2
%define SECTOR_NUM_PORT 0x1f3
%define CYLINDER_LOW_PORT 0x1f4
%define CYLINDER_HIGH_PORT 0x1f5
%define COMMAND_PORT 0x1f7
%define STATUS_REGISTER 0x1f7
%define SLAVE_BIT 0

read_ata_CHS:
    ; selecting master drive
    mov dx, ATA_DRIVE_HEAD_PORT
    mov al, (0xA0 | (SLAVE_BIT << 4) | 0x0)  ; head number 0, slavebit is 0 to indicate selected drive is master
    out dx, al

    ; waiting 400 ns by looping fifteen times?

.init_loop:
    mov cx, 0xf
    mov dx, STATUS_REGISTER

.wait:
    in al, dx
    cmp cx, 0
    je .check_bsy
    loop .wait

.check_bsy:
    and al, 0b10000000
    cmp al, 0
    je drive_ready

drive_error:
    hlt

drive_ready:
    ; we know that memory upto 0x9200 (excluding upper limit) has been read in 1st stage loader
    ; sectors 2 to 11 have been read (inclusive range), we need to read upto 63 sectors
    ; hence we need to read 63 - 12 + 1 = 52 sectors to read from range (12, 63)

    mov dx, SECTOR_COUNT_PORT
    mov al, 52

    out dx, al

    mov dx, SECTOR_NUM_PORT
    mov al, 12

    out dx, al

    mov dx, CYLINDER_LOW_PORT
    xor al, al

    out dx, al

    mov dx, CYLINDER_HIGH_PORT
    xor al, al

    out dx, al

    mov dx, COMMAND_PORT
    mov al, 0x20

    out dx, al  ; sending read sectors command

.check_data_transfer:
    in al, dx
    shr al, 3                   ; checking if DRQ bit is set
    and al, 1
    cmp al, 0
    je .check_data_transfer


    mov rax, 512/2  ; 256 words
    xor bx, bx
    mov bx, 52
    mul bx  ; 256 * 52 words to read
    mov rcx, rax
    mov rdi, 0x9200 ; reading data to [0x9200]
    mov rdx, READ_PORT
    rep insw

    jmp $