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  1. -------------------------------------------------------------------------------------------------------------------------------------------
  2. Multiple CPU Assembly Mnemonic Table v0.1 210299/GPZ-HIT
  3. -------------------------------------------------------------------------------------------------------------------------------------------
  4.  
  5. Registers:
  6. ----------
  7.  
  8. A : akku
  9. F : flag-register
  10.  
  11. B,C,D,E,H,L : 8080/z80 registers
  12. X,Y : 6502/6510 index registers
  13.  
  14. SP : 8080/z80 Stack Pointer
  15. AF,BC,DE,HL : 8080/z80 register pairs
  16.  
  17. PSW : alias for the AF register pair on 8080
  18. M : alias for the HL register pair on 8080
  19.  
  20. Flags:
  21. ------
  22.  
  23. Z : zero flag
  24. C : carry flag
  25. H : 8080/z80 half-carry flag (carry from least significant nibble)
  26. N : 6502 negative (sign) flag
  27. 8080/z80 substract flag (?!)
  28.  
  29. Arguments:
  30. ----------
  31.  
  32. x8 : 8 bit constant that is implied with the opcode
  33.  
  34. p8 : 8 bit Port-Address
  35.  
  36. r8,r8' : one of the 8 bit registers
  37. r16,r16' : one of the register-pairs/16 bit registers
  38.  
  39. m8,m8' : 8 bit memory adress or offset (eg zeropage adressing modes)
  40. i8,i8' : 8 bit immediate value
  41.  
  42. m16,m16' : 16 bit memory adress
  43. i16,i16' : 16 bit immediate value
  44.  
  45. markers:
  46. --------
  47.  
  48. ~ : opcode doesnt exactly match the comparison
  49. * : opcode is undocumented ('illegal')
  50.  
  51. -------------------------------------------------------------------------------------------------------------------------------------------
  52.  
  53. Gameboy note:
  54. -------------
  55.  
  56. zero-page location: $ff00-$ffff (only $ff80-$ffff useable)
  57. stack-location: set by user, SP after reset: $ffff
  58. opcode-syntax referring to: Rednex Gameboy Development System (asMotor of RGBDS)
  59.  
  60. 6502 note:
  61. ----------
  62.  
  63. since there is no HL register for pointers, absolute memory adresses are used
  64. instead. Also 6502 cpu's dont have the (limited) support for 16-bit stuff like
  65. some other 8 bit cpu's (aka register-pairs) so respective opcodes work in 8 bit
  66. only.
  67.  
  68. zero-page location: $0000-$00ff (only $0002-$00ff useable)
  69. stack-location: $0100-$01ff (fixed), SP after reset: $01ff
  70. opcode-syntax referring to: Omikron Turbo Assembler (c64)
  71.  
  72. -------------------------------------------------------------------------------------------------------------------------------------------
  73.  
  74.  
  75. 8080 Z80 Gameboy(~z80) 6502/6510
  76. ------ ------ --------------- -----------
  77.  
  78. loading/storing data:
  79. ---------------------
  80. MVI r8 [i8] LD r8, i8 LD r8, i8 LDA #i8 / LDX #i8 / LDY #i8
  81. MOV r8, r8' LD r8, r8' LD r8, r8' TAX / TXA / TAY / TYA / TXS / TSX
  82.  
  83. LDA [m8] [m8'] LD A, (m16) LD A, [m16] LDA m16
  84. LDAX B LD A, (BC) LD A, [BC] -
  85. LDAX D LD A, (DE) LD A, [DE] -
  86. LHLD [m8] [m8'] LD HL, (m16) LD HL, [m16] -
  87. LXI B [i8] [i8'] LD BC, i16 LD BC, i16 -
  88. LDID [i8] [i8'] LD DE, i16 LD DE, i16 -
  89. LXI H [i8] [i8'] LD HL, i16 LD HL, i16 -
  90.  
  91. STA [m8] [m8'] LD (m16), A LD [m16], A STA m16
  92. SHLD [m8] [m8'] LD (m16), HL LD [m16], HL -
  93. STAX B LD (BC), A LD [BC], A -
  94. STAX D LD (DE), A LD [DE], A -
  95.  
  96. MOV M, r8 LD (HL), r8 LD [HL], r8 -
  97. MOV r8, M LD r8, (HL) LD r8, [HL] -
  98.  
  99. MVI M [i8] LD (HL), i8 LD [HL], i8 -
  100.  
  101. store via HL and inc. HL - - LDI [HL],A -
  102. load via HL and inc. HL - - LDI A,[HL] -
  103.  
  104. store via HL and dec. HL - - LDD [HL],A -
  105. load via HL and dec. HL - - LDD A,[HL] -
  106.  
  107. load from zeropage - - LDH A,[$ff00+m8] LDA $00+m8
  108. store to zeropage - - LDH [$ff00+m8],A STA $00+m8
  109.  
  110. load indexed from zeropage - - LD A,[$ff00+C] LDA $00,Y
  111. store indexed to zeropage - - LD [$ff00+C],A STA $00,Y
  112.  
  113.  
  114. logical instructions:
  115. ---------------------
  116. logical AND ANA M AND (HL) AND [HL] ~AND m16
  117. " ANA r8 AND r8 AND r8 -
  118. " ANI [i8] AND i8 AND i8 AND #i8
  119. logical OR ORA M OR (HL) OR [HL] ~OR m16
  120. " ORA r8 OR r8 OR r8 -
  121. " ORI [i8] OR i8 OR i8 ORA #i8
  122. logical EXCLUSIVE OR XRA M XOR (HL) XOR [HL] ~EOR m16
  123. " XRA r8 XOR r8 XOR r8 -
  124. " XRI [i8] XOR i8 XOR i8 EOR #i8
  125.  
  126. arithmetic instructions:
  127. ------------------------
  128. dec. byte in memory - - DEC [HL] ~DEC m16
  129. dec. register DCR r8 DEC r8 DEC r8 DEX / DEY
  130. dec. register-pair DCX B DEC BC DEC BC -
  131. " DCX D DEC DE DEC DE -
  132. " DCX H DEC HL DEC HL -
  133.  
  134. inc. byte in memory INR M INC (HL) INC [HL] ~INC m16
  135. inc. register INR r8 INC r8 INC r8 INX / INY
  136. inc. register-pair INX B INC BC INC BC -
  137. " INX D INC DE INC DE -
  138. " INX H INC HL INC HL -
  139.  
  140. add with carry ACI [i8] ADC A, i8 ADC A, i8 ADC #i8
  141. " ADC M ADC A, (HL) ADC A, [HL] ~ADC m16
  142. " ADC r8 ADC A, r8 ADC A, r8 -
  143.  
  144. add ADD M ADD A, (HL) ADD A, [HL] ~CLC ; ADC m16
  145. " ADD r8 ADD A, r8 ADD A, r8 -
  146. " ADI [i8] ADD A, i8 ADD A, i8 CLC ; ADC #i8
  147. " DAD B ADD HL, BC ADD HL, BC -
  148. " DAD D ADD HL, DE ADD HL, DE -
  149. " DAD H ADD HL, HL ADD HL, HL -
  150.  
  151. substract with carry SBB M SBC A, (HL) SBC A, [HL] SBC m16
  152. " SBB r8 SBC A, r8 SBC A, r8 -
  153. " SBI [i8] SBC A, i8 SBC A, i8 SBC #i8
  154.  
  155. substract SUB M SUB (HL) SUB [HL] ~SEC ; SBC m16
  156. " SUB r8 SUB r8 SUB r8 -
  157. " SUI [i8] SUB i8 SUB i8 SEC ; SBC #i8
  158.  
  159.  
  160. compares:
  161. ---------
  162. comp. with memory CMP M CP (HL) CP [HL] ~CMP m16
  163. comp. with register CMP r8 CP r8 CP r8 -
  164. comp. with immediate byte CPI [i8] CP i8 CP i8 CMP #i8
  165.  
  166. bit-shifts:
  167. -----------
  168. shift left with Carry RAL RLA RLA ROL A
  169. " - - RL r8 -
  170. shift right with Carry RAR RRA RRA ROR A
  171. " - - RR r8 -
  172. shift left - - SLA ASL A
  173. shift right - - SRL LSR A
  174. RLC RLCA RLCA -
  175. - - RLC r8 -
  176. RRC RRCA RRCA -
  177. - - RRC r8 -
  178. - - SRA -
  179.  
  180. misc operations on registers:
  181. -----------------------------
  182. Complement A CMA CPL CPL EOR #$ff
  183. Decimal Adjust A DAA DAA DAA -
  184. Swap low and high nibble - - SWAP r8 -
  185. exchange DE and HL XCHG EX DE, HL - -
  186.  
  187. setting/resetting flags:
  188. ------------------------
  189. Set Carry Flag STC SCF SCF SEC
  190. Clear Carry Flag STC ; CMC SCF ; CCF SCF ; CCF CLC
  191. Complement Carry Flag CMC CCF CCF -
  192.  
  193. far branch:
  194. -----------
  195. jump to address JMP [m8] [m8'] JP m16 JP m16 JMP m16
  196. jump indirekt via pointer PCHL JP (HL) JP [HL] ~JMP (m16)
  197.  
  198. far conditional branch:
  199. -----------------------
  200. branch if Z==1 JZ [m8] [m8'] JP Z, m16 JP Z, m16 BNE *+3 ; JMP m16
  201. Z==0 JNZ [m8] [m8'] JP NZ, m16 JP NZ, m16 BEQ *+3 ; JMP m16
  202. C==1 JC [m8] [m8'] JP C, m16 JP C, m16 BCC *+3 ; JMP m16
  203. C==0 JNC [m8] [m8'] JP NC, m16 JP NC, m16 BCS *+3 ; JMP m16
  204. JM [m8] [m8'] JP M, m16 - -
  205. JP [m8] [m8'] JP P, m16 - -
  206. JPE [m8] [m8'] JP PE, m16 - -
  207. JPO [m8] [m8'] JP PO, m16 - -
  208.  
  209. near conditional branch:
  210. ------------------------
  211. branch if Z==1 - - JR Z, m16 BEQ m16
  212. Z==0 - - JR NZ, m16 BNE m16
  213. C==1 - - JR C, m16 BCS m16
  214. C==0 - - JR NC, m16 BCC m16
  215. - - - -
  216. - - - -
  217. - - - -
  218. - - - -
  219.  
  220. subroutine call:
  221. ----------------
  222. CALL [m8] [m8'] CALL m16 CALL m16 JSR m16
  223.  
  224. conditional subroutine call:
  225. ----------------------------
  226. call if Z==1 CZ [m8] [m8'] CALL Z, m16 CALL Z, m16 BNE *+3 ; JSR m16
  227. Z==0 CNZ [m8] [m8'] CALL NZ, m16 CALL NZ, m16 BEQ *+3 ; JSR m16
  228. C==1 CC [m8] [m8'] CALL C, m16 CALL C, m16 BCC *+3 ; JSR m16
  229. C==0 CNC [m8] [m8'] CALL NC, m16 CALL NC, m16 BCS *+3 ; JSR m16
  230. CM [m8] [m8'] CALL M, m16 - -
  231. CP [m8] [m8'] CALL P, m16 - -
  232. CPE [m8] [m8'] CALL PE, m16 - -
  233. CPO [m8] [m8'] CALL PO ,m16 - -
  234.  
  235. subroutine return:
  236. ------------------
  237. RET RET RET RTS
  238.  
  239. conditional subroutine return:
  240. ------------------------------
  241. return if Z==1 RZ RET Z RET Z BNE *+1 ; RTS
  242. Z==0 RNZ RET NZ RET NZ BEQ *+1 ; RTS
  243. C==1 RC RET C RET C BCC *+1 ; RTS
  244. C==0 RNC RET NC RET NC BCS *+1 ; RTS
  245. RM RET M - -
  246. RP RET P - -
  247. RPE RET PE - -
  248. RPO RET PO - -
  249.  
  250. interupt related instructions:
  251. ------------------------------
  252. set irq flag (irq's off) DI DI DI SEI
  253. clear irq flag (irq's on) EI EI EI CLI
  254. issue a hard irq RST RST x8 RST x8 BRK
  255.  
  256. i/o specific:
  257. -------------
  258. Get Byte from In-Port IN [p8] IN A, (p8) - -
  259. Send Byte to Out-Port OUT [p8] OUT (p8), A - -
  260.  
  261. stack related:
  262. --------------
  263. put reg. on Stack PUSH B PUSH BC PUSH BC -
  264. PUSH D PUSH DE PUSH DE -
  265. PUSH H PUSH HL PUSH HL -
  266. PUSH PSW PUSH AF PUSH AF PHA ; PHP
  267.  
  268. get reg. from Stack POP B POP BC POP BC -
  269. POP D POP DE POP DE -
  270. POP H POP HL POP HL -
  271. POP PSW POP AF POP AF PLP ; PLA
  272.  
  273. load Stack Pointer LXI SP [i8] [i8'] LD SP, i16 LD SP, i16 LDX #i8 ; TXS
  274. SPHL LD SP, HL LD SP, HL -
  275. - - LD [m16], SP -
  276. - - LD HL,SP+n -
  277.  
  278. dec. Stack-Pointer DCX SP DEC SP DEC SP TSX ; DEX ; TXS
  279. inc. Stack-Pointer INX SP INC SP INC SP TSX ; INX ; TXS
  280.  
  281. DAD SP ADD HL, SP ADD HL, SP -
  282. add to Stack-Pointer - - ADD SP, i8 TSX ; TXA ; CLC ; ADC #i8 ; TAX ; TXS
  283.  
  284. XTHL EX (SP), HL - -
  285.  
  286. misc:
  287. -----
  288. No Operation (Delay) NOP NOP NOP NOP
  289. halt operation (until irq) HALT HLT HLT *JAM
  290. stop cpu (until exception) - - STOP *JAM
  291.  
  292. -------------------------------------------------------------------------------------------------------------------------------------------
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