Double-dabble y 7 segmentos

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:  Universidad de Sevilla
// Engineer: Miguel Angel Rodriguez Jodar
//
// Create Date:    18:05:17 11/13/2013
// Design Name:
// Module Name:    bcd7seg
// Project Name:
// Target Devices: Basys2
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: (C)2013 Miguel Angel Rodriguez Jodar. Todos los derechos reservados
//
//////////////////////////////////////////////////////////////////////////////////
module bcd7seg (
    input wire [4:0] d,
    output wire [7:0] seg
    );

    reg [6:0] tabla[0:15];
    initial begin
        tabla[0]  = 7'b0111111;
        tabla[1]  = 7'b0000110;
        tabla[2]  = 7'b1011011;
        tabla[3]  = 7'b1001111;
        tabla[4]  = 7'b1100110;
        tabla[5]  = 7'b1101101;
        tabla[6]  = 7'b1111101;
        tabla[7]  = 7'b0000111;
        tabla[8]  = 7'b1111111;
        tabla[9]  = 7'b1101111;
        tabla[10] = 7'b1110111;
        tabla[11] = 7'b1111100;
        tabla[12] = 7'b0111001;
        tabla[13] = 7'b1011110;
        tabla[14] = 7'b1111001;
        tabla[15] = 7'b1110001;
    end

    assign seg = {~d[4],~tabla[d[3:0]]};
endmodule

module display (
    input wire clk,
    input wire [15:0] d,
    input wire [3:0] dp,
    output wire [3:0] an,
    output wire [7:0] seg
    );

    reg [3:0] anodo = 4'b0111;
    always @(posedge clk)
        anodo <= {anodo[0],anodo[3:1]};

    assign an = anodo;
    bcd7seg conversor ( !anodo[3]? {dp[3], d[15:12]} :
                        !anodo[2]? {dp[2], d[11:8]} :
                              !anodo[1]? {dp[1], d[7:4]} :
                              !anodo[0]? {dp[0], d[3:0]} :
                                        5'b00000 ,
                              seg);
endmodule

module binary2bcd (
   input wire clk,
   input wire [7:0] n,
   input wire start,
   output wire [11:0] bcd,
   output reg finish
   );

   reg [3:0] loop = 4'h0;
   reg [19:0] scratch = 20'h00000;
   reg [19:0] scratch_modificado;
   reg [11:0] output_reg = 12'h000;
   assign bcd = output_reg;

   always @(posedge clk) begin
      if (start) begin
         loop <= 4'h0;
         scratch <= {12'h000, n};
         finish <= 1'b0;
      end
      else if (loop == 4'd8) begin
         output_reg <= scratch[19:8];
         loop <= loop + 1;
         finish <= 1'b1;
      end
      else if (loop == 4'd9) begin
         finish <= 1'b0;
      end
      else begin
         loop <= loop + 1;
         scratch <= {scratch_modificado[18:0],1'b0};
      end
   end

   always @* begin
      scratch_modificado[7:0] = scratch[7:0];
      if (scratch[11:8]>4)
         scratch_modificado[11:8] = scratch[11:8] + 4'd3;
      else
         scratch_modificado[11:8] = scratch[11:8];
      if (scratch[15:12]>4)
         scratch_modificado[15:12] = scratch[15:12] + 4'd3;
      else
         scratch_modificado[15:12] = scratch[15:12];
      if (scratch[19:16]>4)
         scratch_modificado[19:16] = scratch[19:16] + 4'd3;
      else
         scratch_modificado[19:16] = scratch[19:16];
   end
endmodule