VHDL_lab2

ENTITY mux IS
    GENERIC(del: TIME :=10 ns);
    PORT(a,b:IN BIT;
                s: IN BIT;
                f: OUT BIT);
END;
ARCHITECTURE behave OF mux IS
BEGIN
    PROCESS(a,b,s)
    BEGIN
        IF s='0' THEN
                f<=a AFTER del;
        ELSIF s='1' THEN
                f<=b AFTER del;
        END IF;
    END PROCESS;
END;

ENTITY test_bench IS
END;
ARCHITECTURE struct
OF test_bench IS
COMPONENT mux IS
     GENERIC(del: TIME :=10 ns);
    PORT(a,b:IN BIT;
                s: IN BIT;
                f: OUT BIT);
END COMPONENT;

SIGNAL as,bs,fs,ss: BIT;
BEGIN
l: mux PORT MAP(a=>as,b=>bs,s=>ss,f=>fs);
ss<='0','1' AFTER 500 ns , '0' AFTER 1000 ns, '1' AFTER 1500 ns;
as<='1';
bs<='0';
END;