shift_reg_tb

`timescale 1ns / 1ps
module shift_reg_tb;

reg clock, rst, en, mux_ld;
reg[31:0] inp;
wire outp;

shift_reg shft_reg(
    .clk (clock),
    .reset (rst),
    .enable (en),
    .inp (inp),
    .mux_load(mux_ld),
    .s_out (outp)
);

integer i;
initial begin
    i = 0;

    inp = 32'haaaa;
    clock = 0;
    rst = 0;
    mux_ld = 1;
    en = 0;
    #5 clock = ~clock;
    #5 clock = ~clock;

    mux_ld = 0;
    en = 1;

     for (i = 0 ; i < 20 ; i = i + 1) begin
        #5 clock = ~clock;
        #5 clock = ~clock;
        $display("Shifted val:%b", shft_reg.shifted_reg);
        $display("Shifted reg:%b", shft_reg.s_out);
    end
    $stop;

end
endmodule