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Lauda

Untitled

Nov 16th, 2012
90
0
Never
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VHDL 0.83 KB | None | 0 0
  1. process(iW, sStanje) begin
  2.     case sStanje is
  3.         when S0 =>
  4.             case iW is
  5.                 when "00" => sSledece_Stanje <= S2; oZ <= '0';
  6.                 when "01" => sSledece_Stanje <= S1; oZ <= '0';
  7.                 when "10" => sSledece_Stanje <= S2; oZ <= '1';
  8.                 when others => sSledece_Stanje <= S1; oZ <= '0';
  9.             end case;
  10.            
  11.         when S1 =>
  12.             case iW is
  13.                 when "00" => sSledece_Stanje <= S2; oZ <= '0';
  14.                 when "01" => sSledece_Stanje <= S0; oZ <= '1';
  15.                 when "10" => sSledece_Stanje <= S1; oZ <= '0';
  16.                 when others => sSledece_Stanje <= S1; oZ <= '0';
  17.             end case;
  18.            
  19.         when S2 =>
  20.             case iW is
  21.                 when "00" => sSledece_Stanje <= S0; oZ <= '0';
  22.                 when "01" => sSledece_Stanje <= S0; oZ <= '1';
  23.                 when "10" => sSledece_Stanje <= S1; oZ <= '1';
  24.                 when others => sSledece_Stanje <= S1; oZ <= '0';
  25.             end case;
  26.            
  27.         end case;
  28.     end process;
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