module fulladder_tb();
    logic a,b,c_in;
    logic s,c_out;
fulladder uut(a,b,c_in,s,c_out);
initial
    begin
    a=0;b=0;c_in=0;
    #10 a=0;b=0;c_in=1;
    #10 a=0;b=1;c_in=0;
    #10 a=0;b=1;c_in=1;
    #10 a=1;b=0;c_in=0;
    #10 a=1;b=0;c_in=1;
    #10 a=1;b=1;c_in=0;
    #10 a=1;b=1;c_in=1;
    #10;
    $finish;
    end
endmodule