Signal svetlo

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.ALL;

entity Signal_light is port (
    iCLK    : in  std_logic;
    iRST    : in  std_logic;
    iLEFT   : in  std_logic;
    iRIGHT      : in  std_logic;
    oLEFT       : out std_logic_vector(2 downto 0);
    oRIGHT  : out std_logic_vector(2 downto 0)
    );
end entity;

architecture Behavioral of Signal_light is
type tSTATE is (IDLE,R1,R2,R3,L1,L2,L3);
signal sSTATE,sNEXT_STATE: tSTATE;
signal sR_TC : std_logic;
signal sL_TC : std_logic;
signal sRST_L : std_logic;
signal sRST_R : std_logic;
signal sL_EN : std_logic;
signal sR_EN : std_logic;
signal sR_CNT: std_logic_vector(3 downto 0);
signal sL_CNT: std_logic_vector (3 downto 0);

begin

--registar stanja
process(iRST,iCLK) begin
if(iRST='1') then
sSTATE<=IDLE;
elsif(rising_edge(iCLK)) then
  sSTATE<=sNEXT_STATE;
end if;
end process;

--funkcija prelaza

process(sSTATE,iLEFT,iRIGHT,sL_TC,sR_TC) begin

case(sSTATE) is
      when IDLE=>
                        if(iLEFT='1') then
                         sNEXT_STATE<=L1;
                         elsif(iRIGHT='1') then
                         sNEXT_STATE<=R1;
                         else
                           sNEXT_STATE<=sSTATE;
                            end if;

        when L1=>
                    if(iLEFT='1' and sL_TC='1') then
                           sNEXT_STATE<=L2;
                        elsif(iLEFT='0') then
                           sNEXT_STATE<=IDLE;
                        else
                             sNEXT_STATE<=sSTATE;
                        end if;
        when L2=>
                     if(iLEFT='1' and sL_TC='1') then
                           sNEXT_STATE<=L3;
                        elsif(iLEFT='0') then
                           sNEXT_STATE<=IDLE;
                        else
                             sNEXT_STATE<=sSTATE;
                        end if;
       when L3=>
                    if(sL_TC='1' or iLEFT='0')then
                         sNEXT_STATE<=IDLE;
                         else
                           sNEXT_STATE<=sSTATE;
                            end if;
          when R1=>
                    if(iRIGHT='1' and sR_TC='1') then
                          sNEXT_STATE<=R2;
                          elsif(iRIGHT='0') then
                           sNEXT_STATE<=IDLE;
                          else
                               sNEXT_STATE<=sSTATE;
                            end if;
        when R2=>
                   if(iRIGHT='1' and sR_TC='1') then
                          sNEXT_STATE<=R3;
                          elsif(iRIGHT='0') then
                           sNEXT_STATE<=IDLE;
                          else
                               sNEXT_STATE<=sSTATE;
                            end if;
        when R3=>
                   if(sR_TC='1' or iRIGHT='0') then
                          sNEXT_STATE<=IDLE;
                        else
                             sNEXT_STATE<=sSTATE;
                            end if;
        when others=>
                    sNEXT_STATE<=sSTATE;
        end case;
end process;

--funkcija izlaza

oLEFT<="001" when sSTATE=L1 else
       "011" when sSTATE=L2 else
         "111" when sSTATE=L3 else
         "000";
oRIGHT<="100" when sSTATE=R1 else
       "110" when sSTATE=R2 else
         "111" when sSTATE=R3 else
         "000";
sL_EN<='1' when sSTATE=L1 or sSTATE=L2 or sSTATE=L3 else '0';
sR_EN<='1' when sSTATE=R1 or sSTATE=R2 or sSTATE=R3 else '0';
sRST_L<='1' when sSTATE=IDLE or sSTATE=R1 or sSTATE=R2 or sSTATE=R3 else '0';
sRST_R<='1' when sSTATE=IDLE or sSTATE=L1 or sSTATE=L2 or sSTATE=L3 else '0';

--LEVI brojac po modulu 10
process(iCLK,iRST) begin

if(iRST='1') then
sL_CNT<="0000";
elsif(rising_edge(iCLK)) then
    if(sRST_L='1') then
         sL_CNT<="1001";
         elsif(sL_EN='1') then
        if(sL_CNT="00000") then
           sL_CNT<="1001";
        else
          sL_CNT<= sL_CNT-1;
            end if;
 end if;
end if;

end process;
sL_TC<='1' when sL_CNT="0000" else '0';

--DESNI brojac po modulu 10

process( iCLK,iRST) begin

if(iRST='1') then
sR_CNT<="0000";
elsif(rising_edge(iCLK)) then
   if(sRST_R='1') then
      sR_CNT<="1001";
    elsif(sR_EN='1') then
         if(sR_CNT=0) then
              sR_CNT<="1001";
            else
               sR_CNT<=sR_CNT-1;
            end if;
end if;
end if;

end process;
sR_TC<='1' when sR_CNT="0000" else '0';


end Behavioral;