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Wielder2927

thread execution

Jan 19th, 2024
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SystemVerilog 0.38 KB | Source Code | 0 0
  1. module tb;
  2.   parameter time CYCLE = 10ns;
  3.  
  4.   logic clk;
  5.  
  6.   initial begin
  7.     clk <= 0;
  8.  
  9.     forever begin
  10.       #(CYCLE/2) clk ^= 1'b1;
  11.     end
  12.   end
  13.  
  14.   always @(posedge clk) begin
  15.     clk = 0;
  16.     $display("first thread");
  17.   end
  18.  
  19.   always @(posedge clk) begin
  20.     clk = 0;
  21.     $display("second thread");
  22.   end
  23.  
  24.   initial begin
  25.     #1000ns;
  26.     $stop;
  27.   end
  28. endmodule
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