ac lab4 pb1&2

module fac(input x, y, ci,
           output co, z);
    assign {co,z}=x+y+ci;
endmodule

module fac_tb;
    reg x, y, ci;
    wire z, co;
    fac cut(.x(x), .y(y), .ci(ci), .co(co), .z(z));
    integer k;
    initial begin
        $display("Time\tx\ty\tci\t\tco\tz");
        $monitor("%0t\t%b\t%b\t%b\t\t%b\t%b", $time, x, y, ci, co, z);
        for (k = 0; k < 8; k = k + 1) begin
            {x,y,ci} = k;
            #10;
        end
    end
endmodule