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  1. --------------------------------------------------------------------------------
  2. Release 14.4 Trace (lin64)
  3. Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
  4.  
  5. /home/calros/Xilinx/14.4/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3
  6. -s 1 -n 3 -fastpaths -xml vedic_div32.twx vedic_div32.ncd -o vedic_div32.twr
  7. vedic_div32.pcf -ucf vedic_div32.ucf
  8.  
  9. Design file: vedic_div32.ncd
  10. Physical constraint file: vedic_div32.pcf
  11. Device,package,speed: xc5vlx50t,ff1136,-1 (PRODUCTION 1.73 2012-12-04, STEPPING level 0)
  12. Report level: verbose report
  13.  
  14. Environment Variable Effect
  15. -------------------- ------
  16. NONE No environment variables were set
  17. --------------------------------------------------------------------------------
  18.  
  19. INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
  20. INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
  21. option. All paths that are not constrained will be reported in the
  22. unconstrained paths section(s) of the report.
  23. INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
  24. a 50 Ohm transmission line loading model. For the details of this model,
  25. and for more information on accounting for different loading conditions,
  26. please see the device datasheet.
  27.  
  28. ================================================================================
  29. Timing constraint: TS_SYS_CLK = PERIOD TIMEGRP "SYS_CLK" 14.52 ns HIGH 50%;
  30. For more information, see Period Analysis in the Timing Closure User Guide (UG612).
  31.  
  32. 43625899728 paths analyzed, 790 endpoints analyzed, 135 failing endpoints
  33. 135 timing errors detected. (135 setup errors, 0 hold errors, 0 component switching limit errors)
  34. Minimum period is 15.831ns.
  35. --------------------------------------------------------------------------------
  36.  
  37. Paths for end point main_reg.re_reg_34 (SLICE_X0Y10.D6), 661689984 paths
  38. --------------------------------------------------------------------------------
  39. Slack (setup path): -1.311ns (requirement - (data path - clock path skew + uncertainty))
  40. Source: state_FSM_FFd4 (FF)
  41. Destination: main_reg.re_reg_34 (FF)
  42. Requirement: 14.520ns
  43. Data Path Delay: 15.785ns (Levels of Logic = 12)
  44. Clock Path Skew: -0.011ns (0.530 - 0.541)
  45. Source Clock: mclk1_BUFGP rising at 0.000ns
  46. Destination Clock: mclk1_BUFGP rising at 14.520ns
  47. Clock Uncertainty: 0.035ns
  48.  
  49. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  50. Total System Jitter (TSJ): 0.070ns
  51. Total Input Jitter (TIJ): 0.000ns
  52. Discrete Jitter (DJ): 0.000ns
  53. Phase Error (PE): 0.000ns
  54.  
  55. Maximum Data Path: state_FSM_FFd4 to main_reg.re_reg_34
  56. Location Delay type Delay(ns) Physical Resource
  57. Logical Resource(s)
  58. ------------------------------------------------- -------------------
  59. SLICE_X15Y5.AQ Tcko 0.450 state_FSM_FFd4
  60. state_FSM_FFd4
  61. SLICE_X10Y1.B6 net (fanout=317) 0.709 state_FSM_FFd4
  62. SLICE_X10Y1.B Tilo 0.094 quo_tmp_mux0000<0>
  63. reg_quo_reg<2>1
  64. SLICE_X11Y1.C4 net (fanout=3) 0.560 reg_quo_reg<2>
  65. SLICE_X11Y1.C Tilo 0.094 N239
  66. Sh17365
  67. SLICE_X14Y4.C4 net (fanout=1) 0.739 Sh17365
  68. SLICE_X14Y4.C Tilo 0.094 Sh117
  69. Sh173138_SW0
  70. SLICE_X14Y4.A6 net (fanout=2) 0.299 N386
  71. SLICE_X14Y4.A Tilo 0.094 Sh117
  72. Sh173138
  73. DSP48_X0Y0.B1 net (fanout=9) 0.703 Sh173
  74. DSP48_X0Y0.PCOUT0 Tdspdo_BPCOUT_M 3.832 Mmult_re_tmp_mult0001
  75. Mmult_re_tmp_mult0001
  76. DSP48_X0Y1.PCIN0 net (fanout=1) 0.000 Mmult_re_tmp_mult0001_PCOUT_to_Mmult_re_tmp_mult00011_PCIN_0
  77. DSP48_X0Y1.PCOUT9 Tdspdo_PCINPCOUT 2.013 Mmult_re_tmp_mult00011
  78. Mmult_re_tmp_mult00011
  79. DSP48_X0Y2.PCIN9 net (fanout=1) 0.000 Mmult_re_tmp_mult00011_PCOUT_to_Mmult_re_tmp_mult00012_PCIN_9
  80. DSP48_X0Y2.P1 Tdspdo_PCINP 1.816 Mmult_re_tmp_mult00012
  81. Mmult_re_tmp_mult00012
  82. SLICE_X5Y6.B3 net (fanout=4) 0.953 re_tmp_mult0001<18>
  83. SLICE_X5Y6.B Tilo 0.094 Sh318
  84. Sh3211
  85. SLICE_X6Y4.D5 net (fanout=5) 0.564 Sh321
  86. SLICE_X6Y4.CMUX Topdc 0.389 Sh341
  87. Sh389_F
  88. Sh389
  89. SLICE_X3Y4.A4 net (fanout=2) 0.668 Sh389
  90. SLICE_X3Y4.COUT Topcya 0.509 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  91. Mcompar_main_reg.re_reg_cmp_gt0000_lut<12>
  92. Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  93. SLICE_X3Y5.CIN net (fanout=1) 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  94. SLICE_X3Y5.AMUX Tcina 0.303 Sh337
  95. Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>
  96. SLICE_X0Y10.D6 net (fanout=37) 0.798 Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>
  97. SLICE_X0Y10.CLK Tas 0.010 main_reg.re_reg_34
  98. main_reg_re_reg_mux0000<34>1
  99. main_reg.re_reg_34
  100. ------------------------------------------------- ---------------------------
  101. Total 15.785ns (9.792ns logic, 5.993ns route)
  102. (62.0% logic, 38.0% route)
  103.  
  104. --------------------------------------------------------------------------------
  105. Slack (setup path): -1.311ns (requirement - (data path - clock path skew + uncertainty))
  106. Source: state_FSM_FFd4 (FF)
  107. Destination: main_reg.re_reg_34 (FF)
  108. Requirement: 14.520ns
  109. Data Path Delay: 15.785ns (Levels of Logic = 12)
  110. Clock Path Skew: -0.011ns (0.530 - 0.541)
  111. Source Clock: mclk1_BUFGP rising at 0.000ns
  112. Destination Clock: mclk1_BUFGP rising at 14.520ns
  113. Clock Uncertainty: 0.035ns
  114.  
  115. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  116. Total System Jitter (TSJ): 0.070ns
  117. Total Input Jitter (TIJ): 0.000ns
  118. Discrete Jitter (DJ): 0.000ns
  119. Phase Error (PE): 0.000ns
  120.  
  121. Maximum Data Path: state_FSM_FFd4 to main_reg.re_reg_34
  122. Location Delay type Delay(ns) Physical Resource
  123. Logical Resource(s)
  124. ------------------------------------------------- -------------------
  125. SLICE_X15Y5.AQ Tcko 0.450 state_FSM_FFd4
  126. state_FSM_FFd4
  127. SLICE_X10Y1.B6 net (fanout=317) 0.709 state_FSM_FFd4
  128. SLICE_X10Y1.B Tilo 0.094 quo_tmp_mux0000<0>
  129. reg_quo_reg<2>1
  130. SLICE_X11Y1.C4 net (fanout=3) 0.560 reg_quo_reg<2>
  131. SLICE_X11Y1.C Tilo 0.094 N239
  132. Sh17365
  133. SLICE_X14Y4.C4 net (fanout=1) 0.739 Sh17365
  134. SLICE_X14Y4.C Tilo 0.094 Sh117
  135. Sh173138_SW0
  136. SLICE_X14Y4.A6 net (fanout=2) 0.299 N386
  137. SLICE_X14Y4.A Tilo 0.094 Sh117
  138. Sh173138
  139. DSP48_X0Y0.B1 net (fanout=9) 0.703 Sh173
  140. DSP48_X0Y0.PCOUT9 Tdspdo_BPCOUT_M 3.832 Mmult_re_tmp_mult0001
  141. Mmult_re_tmp_mult0001
  142. DSP48_X0Y1.PCIN9 net (fanout=1) 0.000 Mmult_re_tmp_mult0001_PCOUT_to_Mmult_re_tmp_mult00011_PCIN_9
  143. DSP48_X0Y1.PCOUT9 Tdspdo_PCINPCOUT 2.013 Mmult_re_tmp_mult00011
  144. Mmult_re_tmp_mult00011
  145. DSP48_X0Y2.PCIN9 net (fanout=1) 0.000 Mmult_re_tmp_mult00011_PCOUT_to_Mmult_re_tmp_mult00012_PCIN_9
  146. DSP48_X0Y2.P1 Tdspdo_PCINP 1.816 Mmult_re_tmp_mult00012
  147. Mmult_re_tmp_mult00012
  148. SLICE_X5Y6.B3 net (fanout=4) 0.953 re_tmp_mult0001<18>
  149. SLICE_X5Y6.B Tilo 0.094 Sh318
  150. Sh3211
  151. SLICE_X6Y4.D5 net (fanout=5) 0.564 Sh321
  152. SLICE_X6Y4.CMUX Topdc 0.389 Sh341
  153. Sh389_F
  154. Sh389
  155. SLICE_X3Y4.A4 net (fanout=2) 0.668 Sh389
  156. SLICE_X3Y4.COUT Topcya 0.509 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  157. Mcompar_main_reg.re_reg_cmp_gt0000_lut<12>
  158. Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  159. SLICE_X3Y5.CIN net (fanout=1) 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  160. SLICE_X3Y5.AMUX Tcina 0.303 Sh337
  161. Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>
  162. SLICE_X0Y10.D6 net (fanout=37) 0.798 Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>
  163. SLICE_X0Y10.CLK Tas 0.010 main_reg.re_reg_34
  164. main_reg_re_reg_mux0000<34>1
  165. main_reg.re_reg_34
  166. ------------------------------------------------- ---------------------------
  167. Total 15.785ns (9.792ns logic, 5.993ns route)
  168. (62.0% logic, 38.0% route)
  169.  
  170. --------------------------------------------------------------------------------
  171. Slack (setup path): -1.311ns (requirement - (data path - clock path skew + uncertainty))
  172. Source: state_FSM_FFd4 (FF)
  173. Destination: main_reg.re_reg_34 (FF)
  174. Requirement: 14.520ns
  175. Data Path Delay: 15.785ns (Levels of Logic = 12)
  176. Clock Path Skew: -0.011ns (0.530 - 0.541)
  177. Source Clock: mclk1_BUFGP rising at 0.000ns
  178. Destination Clock: mclk1_BUFGP rising at 14.520ns
  179. Clock Uncertainty: 0.035ns
  180.  
  181. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  182. Total System Jitter (TSJ): 0.070ns
  183. Total Input Jitter (TIJ): 0.000ns
  184. Discrete Jitter (DJ): 0.000ns
  185. Phase Error (PE): 0.000ns
  186.  
  187. Maximum Data Path: state_FSM_FFd4 to main_reg.re_reg_34
  188. Location Delay type Delay(ns) Physical Resource
  189. Logical Resource(s)
  190. ------------------------------------------------- -------------------
  191. SLICE_X15Y5.AQ Tcko 0.450 state_FSM_FFd4
  192. state_FSM_FFd4
  193. SLICE_X10Y1.B6 net (fanout=317) 0.709 state_FSM_FFd4
  194. SLICE_X10Y1.B Tilo 0.094 quo_tmp_mux0000<0>
  195. reg_quo_reg<2>1
  196. SLICE_X11Y1.C4 net (fanout=3) 0.560 reg_quo_reg<2>
  197. SLICE_X11Y1.C Tilo 0.094 N239
  198. Sh17365
  199. SLICE_X14Y4.C4 net (fanout=1) 0.739 Sh17365
  200. SLICE_X14Y4.C Tilo 0.094 Sh117
  201. Sh173138_SW0
  202. SLICE_X14Y4.A6 net (fanout=2) 0.299 N386
  203. SLICE_X14Y4.A Tilo 0.094 Sh117
  204. Sh173138
  205. DSP48_X0Y0.B1 net (fanout=9) 0.703 Sh173
  206. DSP48_X0Y0.PCOUT1 Tdspdo_BPCOUT_M 3.832 Mmult_re_tmp_mult0001
  207. Mmult_re_tmp_mult0001
  208. DSP48_X0Y1.PCIN1 net (fanout=1) 0.000 Mmult_re_tmp_mult0001_PCOUT_to_Mmult_re_tmp_mult00011_PCIN_1
  209. DSP48_X0Y1.PCOUT9 Tdspdo_PCINPCOUT 2.013 Mmult_re_tmp_mult00011
  210. Mmult_re_tmp_mult00011
  211. DSP48_X0Y2.PCIN9 net (fanout=1) 0.000 Mmult_re_tmp_mult00011_PCOUT_to_Mmult_re_tmp_mult00012_PCIN_9
  212. DSP48_X0Y2.P1 Tdspdo_PCINP 1.816 Mmult_re_tmp_mult00012
  213. Mmult_re_tmp_mult00012
  214. SLICE_X5Y6.B3 net (fanout=4) 0.953 re_tmp_mult0001<18>
  215. SLICE_X5Y6.B Tilo 0.094 Sh318
  216. Sh3211
  217. SLICE_X6Y4.D5 net (fanout=5) 0.564 Sh321
  218. SLICE_X6Y4.CMUX Topdc 0.389 Sh341
  219. Sh389_F
  220. Sh389
  221. SLICE_X3Y4.A4 net (fanout=2) 0.668 Sh389
  222. SLICE_X3Y4.COUT Topcya 0.509 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  223. Mcompar_main_reg.re_reg_cmp_gt0000_lut<12>
  224. Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  225. SLICE_X3Y5.CIN net (fanout=1) 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  226. SLICE_X3Y5.AMUX Tcina 0.303 Sh337
  227. Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>
  228. SLICE_X0Y10.D6 net (fanout=37) 0.798 Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>
  229. SLICE_X0Y10.CLK Tas 0.010 main_reg.re_reg_34
  230. main_reg_re_reg_mux0000<34>1
  231. main_reg.re_reg_34
  232. ------------------------------------------------- ---------------------------
  233. Total 15.785ns (9.792ns logic, 5.993ns route)
  234. (62.0% logic, 38.0% route)
  235.  
  236. --------------------------------------------------------------------------------
  237.  
  238. Paths for end point main_reg.re_reg_2 (SLICE_X1Y0.C6), 661689984 paths
  239. --------------------------------------------------------------------------------
  240. Slack (setup path): -1.307ns (requirement - (data path - clock path skew + uncertainty))
  241. Source: state_FSM_FFd4 (FF)
  242. Destination: main_reg.re_reg_2 (FF)
  243. Requirement: 14.520ns
  244. Data Path Delay: 15.811ns (Levels of Logic = 12)
  245. Clock Path Skew: 0.019ns (0.560 - 0.541)
  246. Source Clock: mclk1_BUFGP rising at 0.000ns
  247. Destination Clock: mclk1_BUFGP rising at 14.520ns
  248. Clock Uncertainty: 0.035ns
  249.  
  250. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  251. Total System Jitter (TSJ): 0.070ns
  252. Total Input Jitter (TIJ): 0.000ns
  253. Discrete Jitter (DJ): 0.000ns
  254. Phase Error (PE): 0.000ns
  255.  
  256. Maximum Data Path: state_FSM_FFd4 to main_reg.re_reg_2
  257. Location Delay type Delay(ns) Physical Resource
  258. Logical Resource(s)
  259. ------------------------------------------------- -------------------
  260. SLICE_X15Y5.AQ Tcko 0.450 state_FSM_FFd4
  261. state_FSM_FFd4
  262. SLICE_X10Y1.B6 net (fanout=317) 0.709 state_FSM_FFd4
  263. SLICE_X10Y1.B Tilo 0.094 quo_tmp_mux0000<0>
  264. reg_quo_reg<2>1
  265. SLICE_X11Y1.C4 net (fanout=3) 0.560 reg_quo_reg<2>
  266. SLICE_X11Y1.C Tilo 0.094 N239
  267. Sh17365
  268. SLICE_X14Y4.C4 net (fanout=1) 0.739 Sh17365
  269. SLICE_X14Y4.C Tilo 0.094 Sh117
  270. Sh173138_SW0
  271. SLICE_X14Y4.A6 net (fanout=2) 0.299 N386
  272. SLICE_X14Y4.A Tilo 0.094 Sh117
  273. Sh173138
  274. DSP48_X0Y0.B1 net (fanout=9) 0.703 Sh173
  275. DSP48_X0Y0.PCOUT0 Tdspdo_BPCOUT_M 3.832 Mmult_re_tmp_mult0001
  276. Mmult_re_tmp_mult0001
  277. DSP48_X0Y1.PCIN0 net (fanout=1) 0.000 Mmult_re_tmp_mult0001_PCOUT_to_Mmult_re_tmp_mult00011_PCIN_0
  278. DSP48_X0Y1.PCOUT9 Tdspdo_PCINPCOUT 2.013 Mmult_re_tmp_mult00011
  279. Mmult_re_tmp_mult00011
  280. DSP48_X0Y2.PCIN9 net (fanout=1) 0.000 Mmult_re_tmp_mult00011_PCOUT_to_Mmult_re_tmp_mult00012_PCIN_9
  281. DSP48_X0Y2.P1 Tdspdo_PCINP 1.816 Mmult_re_tmp_mult00012
  282. Mmult_re_tmp_mult00012
  283. SLICE_X5Y6.B3 net (fanout=4) 0.953 re_tmp_mult0001<18>
  284. SLICE_X5Y6.B Tilo 0.094 Sh318
  285. Sh3211
  286. SLICE_X6Y4.D5 net (fanout=5) 0.564 Sh321
  287. SLICE_X6Y4.CMUX Topdc 0.389 Sh341
  288. Sh389_F
  289. Sh389
  290. SLICE_X3Y4.A4 net (fanout=2) 0.668 Sh389
  291. SLICE_X3Y4.COUT Topcya 0.509 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  292. Mcompar_main_reg.re_reg_cmp_gt0000_lut<12>
  293. Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  294. SLICE_X3Y5.CIN net (fanout=1) 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  295. SLICE_X3Y5.AMUX Tcina 0.303 Sh337
  296. Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>
  297. SLICE_X1Y0.C6 net (fanout=37) 0.805 Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>
  298. SLICE_X1Y0.CLK Tas 0.029 main_reg.re_reg_3
  299. main_reg_re_reg_mux0000<2>1
  300. main_reg.re_reg_2
  301. ------------------------------------------------- ---------------------------
  302. Total 15.811ns (9.811ns logic, 6.000ns route)
  303. (62.1% logic, 37.9% route)
  304.  
  305. --------------------------------------------------------------------------------
  306. Slack (setup path): -1.307ns (requirement - (data path - clock path skew + uncertainty))
  307. Source: state_FSM_FFd4 (FF)
  308. Destination: main_reg.re_reg_2 (FF)
  309. Requirement: 14.520ns
  310. Data Path Delay: 15.811ns (Levels of Logic = 12)
  311. Clock Path Skew: 0.019ns (0.560 - 0.541)
  312. Source Clock: mclk1_BUFGP rising at 0.000ns
  313. Destination Clock: mclk1_BUFGP rising at 14.520ns
  314. Clock Uncertainty: 0.035ns
  315.  
  316. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  317. Total System Jitter (TSJ): 0.070ns
  318. Total Input Jitter (TIJ): 0.000ns
  319. Discrete Jitter (DJ): 0.000ns
  320. Phase Error (PE): 0.000ns
  321.  
  322. Maximum Data Path: state_FSM_FFd4 to main_reg.re_reg_2
  323. Location Delay type Delay(ns) Physical Resource
  324. Logical Resource(s)
  325. ------------------------------------------------- -------------------
  326. SLICE_X15Y5.AQ Tcko 0.450 state_FSM_FFd4
  327. state_FSM_FFd4
  328. SLICE_X10Y1.B6 net (fanout=317) 0.709 state_FSM_FFd4
  329. SLICE_X10Y1.B Tilo 0.094 quo_tmp_mux0000<0>
  330. reg_quo_reg<2>1
  331. SLICE_X11Y1.C4 net (fanout=3) 0.560 reg_quo_reg<2>
  332. SLICE_X11Y1.C Tilo 0.094 N239
  333. Sh17365
  334. SLICE_X14Y4.C4 net (fanout=1) 0.739 Sh17365
  335. SLICE_X14Y4.C Tilo 0.094 Sh117
  336. Sh173138_SW0
  337. SLICE_X14Y4.A6 net (fanout=2) 0.299 N386
  338. SLICE_X14Y4.A Tilo 0.094 Sh117
  339. Sh173138
  340. DSP48_X0Y0.B1 net (fanout=9) 0.703 Sh173
  341. DSP48_X0Y0.PCOUT9 Tdspdo_BPCOUT_M 3.832 Mmult_re_tmp_mult0001
  342. Mmult_re_tmp_mult0001
  343. DSP48_X0Y1.PCIN9 net (fanout=1) 0.000 Mmult_re_tmp_mult0001_PCOUT_to_Mmult_re_tmp_mult00011_PCIN_9
  344. DSP48_X0Y1.PCOUT9 Tdspdo_PCINPCOUT 2.013 Mmult_re_tmp_mult00011
  345. Mmult_re_tmp_mult00011
  346. DSP48_X0Y2.PCIN9 net (fanout=1) 0.000 Mmult_re_tmp_mult00011_PCOUT_to_Mmult_re_tmp_mult00012_PCIN_9
  347. DSP48_X0Y2.P1 Tdspdo_PCINP 1.816 Mmult_re_tmp_mult00012
  348. Mmult_re_tmp_mult00012
  349. SLICE_X5Y6.B3 net (fanout=4) 0.953 re_tmp_mult0001<18>
  350. SLICE_X5Y6.B Tilo 0.094 Sh318
  351. Sh3211
  352. SLICE_X6Y4.D5 net (fanout=5) 0.564 Sh321
  353. SLICE_X6Y4.CMUX Topdc 0.389 Sh341
  354. Sh389_F
  355. Sh389
  356. SLICE_X3Y4.A4 net (fanout=2) 0.668 Sh389
  357. SLICE_X3Y4.COUT Topcya 0.509 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  358. Mcompar_main_reg.re_reg_cmp_gt0000_lut<12>
  359. Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  360. SLICE_X3Y5.CIN net (fanout=1) 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  361. SLICE_X3Y5.AMUX Tcina 0.303 Sh337
  362. Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>
  363. SLICE_X1Y0.C6 net (fanout=37) 0.805 Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>
  364. SLICE_X1Y0.CLK Tas 0.029 main_reg.re_reg_3
  365. main_reg_re_reg_mux0000<2>1
  366. main_reg.re_reg_2
  367. ------------------------------------------------- ---------------------------
  368. Total 15.811ns (9.811ns logic, 6.000ns route)
  369. (62.1% logic, 37.9% route)
  370.  
  371. --------------------------------------------------------------------------------
  372. Slack (setup path): -1.307ns (requirement - (data path - clock path skew + uncertainty))
  373. Source: state_FSM_FFd4 (FF)
  374. Destination: main_reg.re_reg_2 (FF)
  375. Requirement: 14.520ns
  376. Data Path Delay: 15.811ns (Levels of Logic = 12)
  377. Clock Path Skew: 0.019ns (0.560 - 0.541)
  378. Source Clock: mclk1_BUFGP rising at 0.000ns
  379. Destination Clock: mclk1_BUFGP rising at 14.520ns
  380. Clock Uncertainty: 0.035ns
  381.  
  382. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  383. Total System Jitter (TSJ): 0.070ns
  384. Total Input Jitter (TIJ): 0.000ns
  385. Discrete Jitter (DJ): 0.000ns
  386. Phase Error (PE): 0.000ns
  387.  
  388. Maximum Data Path: state_FSM_FFd4 to main_reg.re_reg_2
  389. Location Delay type Delay(ns) Physical Resource
  390. Logical Resource(s)
  391. ------------------------------------------------- -------------------
  392. SLICE_X15Y5.AQ Tcko 0.450 state_FSM_FFd4
  393. state_FSM_FFd4
  394. SLICE_X10Y1.B6 net (fanout=317) 0.709 state_FSM_FFd4
  395. SLICE_X10Y1.B Tilo 0.094 quo_tmp_mux0000<0>
  396. reg_quo_reg<2>1
  397. SLICE_X11Y1.C4 net (fanout=3) 0.560 reg_quo_reg<2>
  398. SLICE_X11Y1.C Tilo 0.094 N239
  399. Sh17365
  400. SLICE_X14Y4.C4 net (fanout=1) 0.739 Sh17365
  401. SLICE_X14Y4.C Tilo 0.094 Sh117
  402. Sh173138_SW0
  403. SLICE_X14Y4.A6 net (fanout=2) 0.299 N386
  404. SLICE_X14Y4.A Tilo 0.094 Sh117
  405. Sh173138
  406. DSP48_X0Y0.B1 net (fanout=9) 0.703 Sh173
  407. DSP48_X0Y0.PCOUT1 Tdspdo_BPCOUT_M 3.832 Mmult_re_tmp_mult0001
  408. Mmult_re_tmp_mult0001
  409. DSP48_X0Y1.PCIN1 net (fanout=1) 0.000 Mmult_re_tmp_mult0001_PCOUT_to_Mmult_re_tmp_mult00011_PCIN_1
  410. DSP48_X0Y1.PCOUT9 Tdspdo_PCINPCOUT 2.013 Mmult_re_tmp_mult00011
  411. Mmult_re_tmp_mult00011
  412. DSP48_X0Y2.PCIN9 net (fanout=1) 0.000 Mmult_re_tmp_mult00011_PCOUT_to_Mmult_re_tmp_mult00012_PCIN_9
  413. DSP48_X0Y2.P1 Tdspdo_PCINP 1.816 Mmult_re_tmp_mult00012
  414. Mmult_re_tmp_mult00012
  415. SLICE_X5Y6.B3 net (fanout=4) 0.953 re_tmp_mult0001<18>
  416. SLICE_X5Y6.B Tilo 0.094 Sh318
  417. Sh3211
  418. SLICE_X6Y4.D5 net (fanout=5) 0.564 Sh321
  419. SLICE_X6Y4.CMUX Topdc 0.389 Sh341
  420. Sh389_F
  421. Sh389
  422. SLICE_X3Y4.A4 net (fanout=2) 0.668 Sh389
  423. SLICE_X3Y4.COUT Topcya 0.509 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  424. Mcompar_main_reg.re_reg_cmp_gt0000_lut<12>
  425. Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  426. SLICE_X3Y5.CIN net (fanout=1) 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  427. SLICE_X3Y5.AMUX Tcina 0.303 Sh337
  428. Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>
  429. SLICE_X1Y0.C6 net (fanout=37) 0.805 Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>
  430. SLICE_X1Y0.CLK Tas 0.029 main_reg.re_reg_3
  431. main_reg_re_reg_mux0000<2>1
  432. main_reg.re_reg_2
  433. ------------------------------------------------- ---------------------------
  434. Total 15.811ns (9.811ns logic, 6.000ns route)
  435. (62.1% logic, 37.9% route)
  436.  
  437. --------------------------------------------------------------------------------
  438.  
  439. Paths for end point main_reg.re_reg_3 (SLICE_X1Y0.D6), 661689984 paths
  440. --------------------------------------------------------------------------------
  441. Slack (setup path): -1.301ns (requirement - (data path - clock path skew + uncertainty))
  442. Source: state_FSM_FFd4 (FF)
  443. Destination: main_reg.re_reg_3 (FF)
  444. Requirement: 14.520ns
  445. Data Path Delay: 15.805ns (Levels of Logic = 12)
  446. Clock Path Skew: 0.019ns (0.560 - 0.541)
  447. Source Clock: mclk1_BUFGP rising at 0.000ns
  448. Destination Clock: mclk1_BUFGP rising at 14.520ns
  449. Clock Uncertainty: 0.035ns
  450.  
  451. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  452. Total System Jitter (TSJ): 0.070ns
  453. Total Input Jitter (TIJ): 0.000ns
  454. Discrete Jitter (DJ): 0.000ns
  455. Phase Error (PE): 0.000ns
  456.  
  457. Maximum Data Path: state_FSM_FFd4 to main_reg.re_reg_3
  458. Location Delay type Delay(ns) Physical Resource
  459. Logical Resource(s)
  460. ------------------------------------------------- -------------------
  461. SLICE_X15Y5.AQ Tcko 0.450 state_FSM_FFd4
  462. state_FSM_FFd4
  463. SLICE_X10Y1.B6 net (fanout=317) 0.709 state_FSM_FFd4
  464. SLICE_X10Y1.B Tilo 0.094 quo_tmp_mux0000<0>
  465. reg_quo_reg<2>1
  466. SLICE_X11Y1.C4 net (fanout=3) 0.560 reg_quo_reg<2>
  467. SLICE_X11Y1.C Tilo 0.094 N239
  468. Sh17365
  469. SLICE_X14Y4.C4 net (fanout=1) 0.739 Sh17365
  470. SLICE_X14Y4.C Tilo 0.094 Sh117
  471. Sh173138_SW0
  472. SLICE_X14Y4.A6 net (fanout=2) 0.299 N386
  473. SLICE_X14Y4.A Tilo 0.094 Sh117
  474. Sh173138
  475. DSP48_X0Y0.B1 net (fanout=9) 0.703 Sh173
  476. DSP48_X0Y0.PCOUT0 Tdspdo_BPCOUT_M 3.832 Mmult_re_tmp_mult0001
  477. Mmult_re_tmp_mult0001
  478. DSP48_X0Y1.PCIN0 net (fanout=1) 0.000 Mmult_re_tmp_mult0001_PCOUT_to_Mmult_re_tmp_mult00011_PCIN_0
  479. DSP48_X0Y1.PCOUT9 Tdspdo_PCINPCOUT 2.013 Mmult_re_tmp_mult00011
  480. Mmult_re_tmp_mult00011
  481. DSP48_X0Y2.PCIN9 net (fanout=1) 0.000 Mmult_re_tmp_mult00011_PCOUT_to_Mmult_re_tmp_mult00012_PCIN_9
  482. DSP48_X0Y2.P1 Tdspdo_PCINP 1.816 Mmult_re_tmp_mult00012
  483. Mmult_re_tmp_mult00012
  484. SLICE_X5Y6.B3 net (fanout=4) 0.953 re_tmp_mult0001<18>
  485. SLICE_X5Y6.B Tilo 0.094 Sh318
  486. Sh3211
  487. SLICE_X6Y4.D5 net (fanout=5) 0.564 Sh321
  488. SLICE_X6Y4.CMUX Topdc 0.389 Sh341
  489. Sh389_F
  490. Sh389
  491. SLICE_X3Y4.A4 net (fanout=2) 0.668 Sh389
  492. SLICE_X3Y4.COUT Topcya 0.509 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  493. Mcompar_main_reg.re_reg_cmp_gt0000_lut<12>
  494. Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  495. SLICE_X3Y5.CIN net (fanout=1) 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  496. SLICE_X3Y5.AMUX Tcina 0.303 Sh337
  497. Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>
  498. SLICE_X1Y0.D6 net (fanout=37) 0.800 Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>
  499. SLICE_X1Y0.CLK Tas 0.028 main_reg.re_reg_3
  500. main_reg_re_reg_mux0000<3>1
  501. main_reg.re_reg_3
  502. ------------------------------------------------- ---------------------------
  503. Total 15.805ns (9.810ns logic, 5.995ns route)
  504. (62.1% logic, 37.9% route)
  505.  
  506. --------------------------------------------------------------------------------
  507. Slack (setup path): -1.301ns (requirement - (data path - clock path skew + uncertainty))
  508. Source: state_FSM_FFd4 (FF)
  509. Destination: main_reg.re_reg_3 (FF)
  510. Requirement: 14.520ns
  511. Data Path Delay: 15.805ns (Levels of Logic = 12)
  512. Clock Path Skew: 0.019ns (0.560 - 0.541)
  513. Source Clock: mclk1_BUFGP rising at 0.000ns
  514. Destination Clock: mclk1_BUFGP rising at 14.520ns
  515. Clock Uncertainty: 0.035ns
  516.  
  517. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  518. Total System Jitter (TSJ): 0.070ns
  519. Total Input Jitter (TIJ): 0.000ns
  520. Discrete Jitter (DJ): 0.000ns
  521. Phase Error (PE): 0.000ns
  522.  
  523. Maximum Data Path: state_FSM_FFd4 to main_reg.re_reg_3
  524. Location Delay type Delay(ns) Physical Resource
  525. Logical Resource(s)
  526. ------------------------------------------------- -------------------
  527. SLICE_X15Y5.AQ Tcko 0.450 state_FSM_FFd4
  528. state_FSM_FFd4
  529. SLICE_X10Y1.B6 net (fanout=317) 0.709 state_FSM_FFd4
  530. SLICE_X10Y1.B Tilo 0.094 quo_tmp_mux0000<0>
  531. reg_quo_reg<2>1
  532. SLICE_X11Y1.C4 net (fanout=3) 0.560 reg_quo_reg<2>
  533. SLICE_X11Y1.C Tilo 0.094 N239
  534. Sh17365
  535. SLICE_X14Y4.C4 net (fanout=1) 0.739 Sh17365
  536. SLICE_X14Y4.C Tilo 0.094 Sh117
  537. Sh173138_SW0
  538. SLICE_X14Y4.A6 net (fanout=2) 0.299 N386
  539. SLICE_X14Y4.A Tilo 0.094 Sh117
  540. Sh173138
  541. DSP48_X0Y0.B1 net (fanout=9) 0.703 Sh173
  542. DSP48_X0Y0.PCOUT9 Tdspdo_BPCOUT_M 3.832 Mmult_re_tmp_mult0001
  543. Mmult_re_tmp_mult0001
  544. DSP48_X0Y1.PCIN9 net (fanout=1) 0.000 Mmult_re_tmp_mult0001_PCOUT_to_Mmult_re_tmp_mult00011_PCIN_9
  545. DSP48_X0Y1.PCOUT9 Tdspdo_PCINPCOUT 2.013 Mmult_re_tmp_mult00011
  546. Mmult_re_tmp_mult00011
  547. DSP48_X0Y2.PCIN9 net (fanout=1) 0.000 Mmult_re_tmp_mult00011_PCOUT_to_Mmult_re_tmp_mult00012_PCIN_9
  548. DSP48_X0Y2.P1 Tdspdo_PCINP 1.816 Mmult_re_tmp_mult00012
  549. Mmult_re_tmp_mult00012
  550. SLICE_X5Y6.B3 net (fanout=4) 0.953 re_tmp_mult0001<18>
  551. SLICE_X5Y6.B Tilo 0.094 Sh318
  552. Sh3211
  553. SLICE_X6Y4.D5 net (fanout=5) 0.564 Sh321
  554. SLICE_X6Y4.CMUX Topdc 0.389 Sh341
  555. Sh389_F
  556. Sh389
  557. SLICE_X3Y4.A4 net (fanout=2) 0.668 Sh389
  558. SLICE_X3Y4.COUT Topcya 0.509 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  559. Mcompar_main_reg.re_reg_cmp_gt0000_lut<12>
  560. Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  561. SLICE_X3Y5.CIN net (fanout=1) 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  562. SLICE_X3Y5.AMUX Tcina 0.303 Sh337
  563. Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>
  564. SLICE_X1Y0.D6 net (fanout=37) 0.800 Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>
  565. SLICE_X1Y0.CLK Tas 0.028 main_reg.re_reg_3
  566. main_reg_re_reg_mux0000<3>1
  567. main_reg.re_reg_3
  568. ------------------------------------------------- ---------------------------
  569. Total 15.805ns (9.810ns logic, 5.995ns route)
  570. (62.1% logic, 37.9% route)
  571.  
  572. --------------------------------------------------------------------------------
  573. Slack (setup path): -1.301ns (requirement - (data path - clock path skew + uncertainty))
  574. Source: state_FSM_FFd4 (FF)
  575. Destination: main_reg.re_reg_3 (FF)
  576. Requirement: 14.520ns
  577. Data Path Delay: 15.805ns (Levels of Logic = 12)
  578. Clock Path Skew: 0.019ns (0.560 - 0.541)
  579. Source Clock: mclk1_BUFGP rising at 0.000ns
  580. Destination Clock: mclk1_BUFGP rising at 14.520ns
  581. Clock Uncertainty: 0.035ns
  582.  
  583. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
  584. Total System Jitter (TSJ): 0.070ns
  585. Total Input Jitter (TIJ): 0.000ns
  586. Discrete Jitter (DJ): 0.000ns
  587. Phase Error (PE): 0.000ns
  588.  
  589. Maximum Data Path: state_FSM_FFd4 to main_reg.re_reg_3
  590. Location Delay type Delay(ns) Physical Resource
  591. Logical Resource(s)
  592. ------------------------------------------------- -------------------
  593. SLICE_X15Y5.AQ Tcko 0.450 state_FSM_FFd4
  594. state_FSM_FFd4
  595. SLICE_X10Y1.B6 net (fanout=317) 0.709 state_FSM_FFd4
  596. SLICE_X10Y1.B Tilo 0.094 quo_tmp_mux0000<0>
  597. reg_quo_reg<2>1
  598. SLICE_X11Y1.C4 net (fanout=3) 0.560 reg_quo_reg<2>
  599. SLICE_X11Y1.C Tilo 0.094 N239
  600. Sh17365
  601. SLICE_X14Y4.C4 net (fanout=1) 0.739 Sh17365
  602. SLICE_X14Y4.C Tilo 0.094 Sh117
  603. Sh173138_SW0
  604. SLICE_X14Y4.A6 net (fanout=2) 0.299 N386
  605. SLICE_X14Y4.A Tilo 0.094 Sh117
  606. Sh173138
  607. DSP48_X0Y0.B1 net (fanout=9) 0.703 Sh173
  608. DSP48_X0Y0.PCOUT1 Tdspdo_BPCOUT_M 3.832 Mmult_re_tmp_mult0001
  609. Mmult_re_tmp_mult0001
  610. DSP48_X0Y1.PCIN1 net (fanout=1) 0.000 Mmult_re_tmp_mult0001_PCOUT_to_Mmult_re_tmp_mult00011_PCIN_1
  611. DSP48_X0Y1.PCOUT9 Tdspdo_PCINPCOUT 2.013 Mmult_re_tmp_mult00011
  612. Mmult_re_tmp_mult00011
  613. DSP48_X0Y2.PCIN9 net (fanout=1) 0.000 Mmult_re_tmp_mult00011_PCOUT_to_Mmult_re_tmp_mult00012_PCIN_9
  614. DSP48_X0Y2.P1 Tdspdo_PCINP 1.816 Mmult_re_tmp_mult00012
  615. Mmult_re_tmp_mult00012
  616. SLICE_X5Y6.B3 net (fanout=4) 0.953 re_tmp_mult0001<18>
  617. SLICE_X5Y6.B Tilo 0.094 Sh318
  618. Sh3211
  619. SLICE_X6Y4.D5 net (fanout=5) 0.564 Sh321
  620. SLICE_X6Y4.CMUX Topdc 0.389 Sh341
  621. Sh389_F
  622. Sh389
  623. SLICE_X3Y4.A4 net (fanout=2) 0.668 Sh389
  624. SLICE_X3Y4.COUT Topcya 0.509 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  625. Mcompar_main_reg.re_reg_cmp_gt0000_lut<12>
  626. Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  627. SLICE_X3Y5.CIN net (fanout=1) 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>
  628. SLICE_X3Y5.AMUX Tcina 0.303 Sh337
  629. Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>
  630. SLICE_X1Y0.D6 net (fanout=37) 0.800 Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>
  631. SLICE_X1Y0.CLK Tas 0.028 main_reg.re_reg_3
  632. main_reg_re_reg_mux0000<3>1
  633. main_reg.re_reg_3
  634. ------------------------------------------------- ---------------------------
  635. Total 15.805ns (9.810ns logic, 5.995ns route)
  636. (62.1% logic, 37.9% route)
  637.  
  638. --------------------------------------------------------------------------------
  639.  
  640. Hold Paths: TS_SYS_CLK = PERIOD TIMEGRP "SYS_CLK" 14.52 ns HIGH 50%;
  641. --------------------------------------------------------------------------------
  642.  
  643. Paths for end point main_reg.re_sign (SLICE_X5Y8.D4), 1 path
  644. --------------------------------------------------------------------------------
  645. Slack (hold path): 0.552ns (requirement - (clock path skew + uncertainty - data path))
  646. Source: main_reg.re_sign (FF)
  647. Destination: main_reg.re_sign (FF)
  648. Requirement: 0.000ns
  649. Data Path Delay: 0.552ns (Levels of Logic = 1)
  650. Clock Path Skew: 0.000ns
  651. Source Clock: mclk1_BUFGP rising at 14.520ns
  652. Destination Clock: mclk1_BUFGP rising at 14.520ns
  653. Clock Uncertainty: 0.000ns
  654.  
  655. Minimum Data Path: main_reg.re_sign to main_reg.re_sign
  656. Location Delay type Delay(ns) Physical Resource
  657. Logical Resource(s)
  658. ------------------------------------------------- -------------------
  659. SLICE_X5Y8.DQ Tcko 0.414 main_reg.re_sign
  660. main_reg.re_sign
  661. SLICE_X5Y8.D4 net (fanout=41) 0.333 main_reg.re_sign
  662. SLICE_X5Y8.CLK Tah (-Th) 0.195 main_reg.re_sign
  663. main_reg.re_sign_rstpot
  664. main_reg.re_sign
  665. ------------------------------------------------- ---------------------------
  666. Total 0.552ns (0.219ns logic, 0.333ns route)
  667. (39.7% logic, 60.3% route)
  668.  
  669. --------------------------------------------------------------------------------
  670.  
  671. Paths for end point main_reg.quo_sign (SLICE_X7Y11.D4), 1 path
  672. --------------------------------------------------------------------------------
  673. Slack (hold path): 0.568ns (requirement - (clock path skew + uncertainty - data path))
  674. Source: main_reg.quo_sign (FF)
  675. Destination: main_reg.quo_sign (FF)
  676. Requirement: 0.000ns
  677. Data Path Delay: 0.568ns (Levels of Logic = 1)
  678. Clock Path Skew: 0.000ns
  679. Source Clock: mclk1_BUFGP rising at 14.520ns
  680. Destination Clock: mclk1_BUFGP rising at 14.520ns
  681. Clock Uncertainty: 0.000ns
  682.  
  683. Minimum Data Path: main_reg.quo_sign to main_reg.quo_sign
  684. Location Delay type Delay(ns) Physical Resource
  685. Logical Resource(s)
  686. ------------------------------------------------- -------------------
  687. SLICE_X7Y11.DQ Tcko 0.414 main_reg.quo_sign
  688. main_reg.quo_sign
  689. SLICE_X7Y11.D4 net (fanout=35) 0.349 main_reg.quo_sign
  690. SLICE_X7Y11.CLK Tah (-Th) 0.195 main_reg.quo_sign
  691. main_reg_quo_sign_mux00001
  692. main_reg.quo_sign
  693. ------------------------------------------------- ---------------------------
  694. Total 0.568ns (0.219ns logic, 0.349ns route)
  695. (38.6% logic, 61.4% route)
  696.  
  697. --------------------------------------------------------------------------------
  698.  
  699. Paths for end point state_FSM_FFd2 (SLICE_X18Y2.B5), 1 path
  700. --------------------------------------------------------------------------------
  701. Slack (hold path): 0.589ns (requirement - (clock path skew + uncertainty - data path))
  702. Source: state_FSM_FFd2 (FF)
  703. Destination: state_FSM_FFd2 (FF)
  704. Requirement: 0.000ns
  705. Data Path Delay: 0.589ns (Levels of Logic = 1)
  706. Clock Path Skew: 0.000ns
  707. Source Clock: mclk1_BUFGP rising at 14.520ns
  708. Destination Clock: mclk1_BUFGP rising at 14.520ns
  709. Clock Uncertainty: 0.000ns
  710.  
  711. Minimum Data Path: state_FSM_FFd2 to state_FSM_FFd2
  712. Location Delay type Delay(ns) Physical Resource
  713. Logical Resource(s)
  714. ------------------------------------------------- -------------------
  715. SLICE_X18Y2.BQ Tcko 0.414 state_FSM_FFd2
  716. state_FSM_FFd2
  717. SLICE_X18Y2.B5 net (fanout=3) 0.358 state_FSM_FFd2
  718. SLICE_X18Y2.CLK Tah (-Th) 0.183 state_FSM_FFd2
  719. state_FSM_FFd2-In1
  720. state_FSM_FFd2
  721. ------------------------------------------------- ---------------------------
  722. Total 0.589ns (0.231ns logic, 0.358ns route)
  723. (39.2% logic, 60.8% route)
  724.  
  725. --------------------------------------------------------------------------------
  726.  
  727. Component Switching Limit Checks: TS_SYS_CLK = PERIOD TIMEGRP "SYS_CLK" 14.52 ns HIGH 50%;
  728. --------------------------------------------------------------------------------
  729. Slack: 12.854ns (period - min period limit)
  730. Period: 14.520ns
  731. Min period limit: 1.666ns (600.240MHz) (Tbgper_I)
  732. Physical resource: mclk1_BUFGP/BUFG/I0
  733. Logical resource: mclk1_BUFGP/BUFG/I0
  734. Location pin: BUFGCTRL_X0Y19.I0
  735. Clock network: mclk1_BUFGP/IBUFG
  736. --------------------------------------------------------------------------------
  737. Slack: 13.702ns (period - (min low pulse limit / (low pulse / period)))
  738. Period: 14.520ns
  739. Low pulse: 7.260ns
  740. Low pulse limit: 0.409ns (Tcl)
  741. Physical resource: main_reg.re_reg_30/CLK
  742. Logical resource: main_reg.re_reg_27/CK
  743. Location pin: SLICE_X0Y9.CLK
  744. Clock network: mclk1_BUFGP
  745. --------------------------------------------------------------------------------
  746. Slack: 13.702ns (period - (min high pulse limit / (high pulse / period)))
  747. Period: 14.520ns
  748. High pulse: 7.260ns
  749. High pulse limit: 0.409ns (Tch)
  750. Physical resource: main_reg.re_reg_30/CLK
  751. Logical resource: main_reg.re_reg_27/CK
  752. Location pin: SLICE_X0Y9.CLK
  753. Clock network: mclk1_BUFGP
  754. --------------------------------------------------------------------------------
  755.  
  756.  
  757. 1 constraint not met.
  758.  
  759.  
  760. Data Sheet report:
  761. -----------------
  762. All values displayed in nanoseconds (ns)
  763.  
  764. Clock to Setup on destination clock mclk1
  765. ---------------+---------+---------+---------+---------+
  766. | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
  767. Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
  768. ---------------+---------+---------+---------+---------+
  769. mclk1 | 15.831| | | |
  770. ---------------+---------+---------+---------+---------+
  771.  
  772.  
  773. Timing summary:
  774. ---------------
  775.  
  776. Timing errors: 135 Score: 91043 (Setup/Max: 91043, Hold: 0)
  777.  
  778. Constraints cover 43625899728 paths, 0 nets, and 5817 connections
  779.  
  780. Design statistics:
  781. Minimum period: 15.831ns{1} (Maximum frequency: 63.167MHz)
  782.  
  783.  
  784. ------------------------------------Footnotes-----------------------------------
  785. 1) The minimum period statistic assumes all single cycle delays.
  786.  
  787. Analysis completed Thu May 7 15:22:13 2015
  788. --------------------------------------------------------------------------------
  789.  
  790. Trace Settings:
  791. -------------------------
  792. Trace Settings
  793.  
  794. Peak Memory Usage: 581 MB
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