Lab09 - Ej03 - Código y Testbench

module rom (input [3:0] address, output [7:0] data);

  reg [7:0] memory [0:15];

  initial
    $readmemb("progROM.list", memory);

  assign data = memory[address];

endmodule

/*
module testbench ();

    reg [3:0] address;
    wire [7:0] data;

    rom U1(address, data);

    initial begin
        $monitor("address: %b  data: %b", address, data);
        for (integer i = 0; i < 16; i++) begin
            #1
            address = i;
        end
    end

endmodule
*/