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SilvanM
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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: ETH Zurich
  4. // Engineer: Frank K. Gurkaynak
  5. //
  6. // Create Date: 18:20:55 03/21/2011
  7. // Design Name:
  8. // Module Name: MIPS
  9. // Project Name: Lab 8
  10. // Target Devices:
  11. // Tool versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21.  
  22. module MIPS(
  23. input CLK, // Clock signal
  24. input RESET, // Reset Active low will set back the Program counter
  25. output [31:0] IOWriteData, // IO Data to be written to the interface
  26. output [3:0] IOAddr, // IO Address we use 4 bits, could also be more
  27. output IOWriteEn, // 1: There is a valid IO Write
  28. input [31:0] IOReadData // 32bit input from the I/O interface
  29. );
  30.  
  31. // The MIPS processor
  32. // (Mostly) based on the descriptions on the textbook
  33. // Digital Design and Computer Architecture
  34. // Chapter 7, Section 7.3, pages 368-381
  35.  
  36. //////////////////////////////////////////////////////////////////////////////////
  37. // Signal Declarations
  38. // Refer to Figure 7.14 page 379 for names
  39.  
  40. // Instruction Decoding
  41. wire [31:0] Instr; // The output of the Instruction memory
  42. wire [31:0] SignImm; // 32-bit extended Immediate value
  43. wire [4:0] WriteReg; // Address of the register for write back
  44.  
  45. // Address controls
  46. reg [31:0] PC; // The Program counter (registered)
  47. wire [31:0] PCbar; // Next state value of the Program counter, PC' in the diagram
  48. wire [31:0] PCCalc; // Calculated value for the (next) PC
  49. wire [31:0] PCJump; // Value for immediate jump
  50. wire [31:0] PCBranch; // Value calculated for the branch instructions
  51. wire [31:0] PCPlus4; // The current value of PC + 4, default next memory address
  52.  
  53. // ALU related
  54. wire [31:0] SrcA; // One input of the ALU
  55. wire [31:0] SrcB; // Other input of the ALU
  56. wire [31:0] ALUResult; // The output of the ALU
  57. wire Zero; // The Zero flag, 1: if ALUResult == 0
  58.  
  59. // Data Memory
  60. wire [31:0] WriteData; // The output of Register File port 2,
  61. wire [31:0] ReadData; // Output of the Data Memory
  62. wire [31:0] Result; // End result that will be written back to register file
  63. wire MemWrite; // Write Enable for the Memory
  64.  
  65. // Control Signals
  66. wire Jump; // A direct jump instruction has been issued
  67. wire MemtoReg; // 1: Copy data from Data Memory to Register File
  68. wire Branch; // 1: We have a branch instruction
  69. wire PCSrc; // We have a Branch AND ALUResult is zero, we will branch
  70. wire [5:0] ALUControl;// Control signals for the ALU
  71. wire ALUSrc; // 0: Register file, 1: Immediate value
  72. wire RegDst; // Destination Register 1: Instr[15:11] 0: Instr[20:15]
  73. wire RegWrite; // 1: We will write back to the RegisterFile
  74.  
  75. // Memory Mapped I/O Signals
  76. wire IsIO; // 1: if Address is in I/O range 0x00007ff0 to 0x0007fff
  77. wire IsMemWrite;// 1: if MemWrite and not IsIO, tells us that we write to memory
  78. // and not to the IO
  79. wire [31:0] ReadMemIO; // Read from either Memory or I/O
  80.  
  81. //////////////////////////////////////////////////////////////////////////////////
  82. // The Main Part of the MIPS processor
  83.  
  84. ////////////////////////////////////
  85. // The Program Counter
  86. always @ ( posedge CLK, posedge RESET )
  87. if (RESET == 1'b1) PC <= 32'h00002FFC; // default program counter
  88. else PC <= PCbar; // Copy next value to present
  89.  
  90. // Calculation of the next PC value
  91. assign PCPlus4 = PC + 4; // By default the PC increments by 4
  92. assign PCBranch = PCPlus4 + {SignImm[29:0],2'b00}; // The branch address see Page 373, Fig 7.10
  93. assign PCCalc = PCSrc ? PCBranch : PCPlus4; // Multiplexer selects Branch or only +4
  94. assign PCJump = {PCPlus4[31:28], Instr[25:0], 2'b00}; // The Jump value
  95. assign PCbar = Jump ? PCJump : PCCalc; // Multiplexer selects Jump or Normal
  96.  
  97. /////////////////////////////////////
  98. // Instantiate the Instruction Memory
  99. InstructionMemory i_imem ( // TODO Part 1
  100. .A(PC[7:2]), //[5:0] // Address of the Instruction max 64 instructions
  101. // Wieso [31:0] PC nach [5:0] A
  102. .RD(Instr) //[31:0] // Value at Address
  103. );
  104.  
  105. // Sign extension, replicate the MSB of the Immediate value
  106. assign SignImm = {{16{Instr[15]}},Instr[15:0]};
  107.  
  108. // Determine the Write Back address for the Register File
  109. assign WriteReg = RegDst ? Instr[15:11] : Instr[20:16];
  110.  
  111. ////////////////////////////////////
  112. // Instantiate the Register File
  113. RegisterFile i_regf (
  114. .A1(Instr[25:21]), // Address for First Register
  115. .A2(Instr[20:16]), // Address for Second Register
  116. .A3(WriteReg), // Address for Write Back
  117. .RD1(SrcA), // First output directly connected to ALU
  118. .RD2(WriteData), // Second output
  119. .WD3(Result), // Output of ALU or Data Memory
  120. .WE3(RegWrite), // From the control unit
  121. .CLK(CLK) // System Clock (10 MHz)
  122. );
  123.  
  124.  
  125. ////////////////////////////////////
  126. // ALU: first determine the inputs, and then instantiate the ALU
  127. assign SrcB = ALUSrc ? SignImm : WriteData ; // ALU input is either immediate or from register
  128.  
  129. ALU i_alu ( // TODO Part 1
  130. .a(SrcA), //[31:0]
  131. .b(SrcB), //[31:0]
  132. .aluop(ALUControl[3:0]), //[3:0]
  133. .result(ALUResult), //[31:0]
  134. .zero(Zero)
  135. );
  136.  
  137. // Generate the PCSrc signal that tells to take the branch
  138. assign PCSrc = Branch & Zero; // simple AND
  139.  
  140. ////////////////////////////////////
  141. // Instantiate the Data Memory
  142. DataMemory i_dmem ( // TODO Part 1
  143. .CLK(CLK), // Clock signal rising edge
  144. .A(ALUResult[7:2]), //[5:0] // Address for 64 locations
  145. .WE(MemWrite), // Write Enable 1: Write 0: no write
  146. .WD(WriteData), //[31:0] // 32-bit data in
  147. .RD(ReadData) //[31:0] // 32-bit read data
  148. );
  149.  
  150. // Memory Mapped I/O
  151. assign IsIO = (ALUResult[31:4] == 28'h00007ff) ? 1 : 0; // 1: whe
  152. // TODO Part 1
  153. assign IsMemWrite = MemWrite & ~IsIO; // Is 1 when there is a SW instruction on DataMem address
  154. assign IOWriteData = WriteData; // This line is connected directly to WriteData
  155. assign IOAddr = ALUResult[3:0]; // The LSB 4 bits of the Address is assigned to IOAddr
  156. assign IOWriteEn = MemWrite & IsIO; // Is 1 when there is a SW instruction on IO address
  157.  
  158.  
  159. assign ReadMemIO = IsIO ? IOReadData : ReadData; // Mux selects memory or I/O
  160. // Select either the Data Memory (or IO) output or the ALU Result
  161. assign Result = MemtoReg ? ReadMemIO : ALUResult; // Slightly modified to include above
  162.  
  163. ////////////////////////////////////
  164. // The Control Unit
  165. ControlUnit i_cont ( // TODO Part 1
  166. .Op(Instr[31:26]), //[5:0]
  167. .Funct(Instr[5:0]), //[5:0]
  168. .Jump(Jump),
  169. .MemtoReg(MemtoReg),
  170. .MemWrite(MemWrite),
  171. .Branch(Branch),
  172. .ALUControl(ALUControl), //[5:0]
  173. .ALUSrc(ALUSrc),
  174. .RegDst(RegDst),
  175. .RegWrite(RegWrite)
  176. );
  177.  
  178.  
  179. endmodule
  180.  
  181. /*module MIPS(
  182. input CLK, // Clock signal
  183. input RESET, // Reset Active low will set back the Program counter
  184. output [31:0] IOWriteData, // IO Data to be written to the interface
  185. output [3:0] IOAddr, // IO Address we use 4 bits, could also be more
  186. output IOWriteEn, // 1: There is a valid IO Write
  187. input [31:0] IOReadData // 32bit input from the I/O interface
  188. );
  189.  
  190. // The MIPS processor
  191. // (Mostly) based on the descriptions on the textbook
  192. // Digital Design and Computer Architecture
  193. // Chapter 7, Section 7.3, pages 368-381
  194.  
  195. //////////////////////////////////////////////////////////////////////////////////
  196. // Signal Declarations
  197. // Refer to Figure 7.14 page 379 for names
  198.  
  199. // Instruction Decoding
  200. wire [31:0] Instr; // The output of the Instruction memory
  201. wire [31:0] SignImm; // 32-bit extended Immediate value
  202. wire [4:0] WriteReg; // Address of the register for write back
  203.  
  204. // Address controls
  205. reg [31:0] PC; // The Program counter (registered)
  206. wire [31:0] PCbar; // Next state value of the Program counter, PC' in the diagram
  207. wire [31:0] PCCalc; // Calculated value for the (next) PC
  208. wire [31:0] PCJump; // Value for immediate jump
  209. wire [31:0] PCBranch; // Value calculated for the branch instructions
  210. wire [31:0] PCPlus4; // The current value of PC + 4, default next memory address
  211.  
  212. // ALU related
  213. wire [31:0] SrcA; // One input of the ALU
  214. wire [31:0] SrcB; // Other input of the ALU
  215. wire [31:0] ALUResult; // The output of the ALU
  216. wire Zero; // The Zero flag, 1: if ALUResult == 0
  217.  
  218. // Data Memory
  219. wire [31:0] WriteData; // The output of Register File port 2,
  220. wire [31:0] ReadData; // Output of the Data Memory
  221. wire [31:0] Result; // End result that will be written back to register file
  222. wire MemWrite; // Write Enable for the Memory
  223.  
  224. // Control Signals
  225. wire Jump; // A direct jump instruction has been issued
  226. wire MemtoReg; // 1: Copy data from Data Memory to Register File
  227. wire Branch; // 1: We have a branch instruction
  228. wire PCSrc; // We have a Branch AND ALUResult is zero, we will branch
  229. wire [5:0] ALUControl;// Control signals for the ALU
  230. wire ALUSrc; // 0: Register file, 1: Immediate value
  231. wire RegDst; // Destination Register 1: Instr[15:11] 0: Instr[20:15]
  232. wire RegWrite; // 1: We will write back to the RegisterFile
  233.  
  234. // Memory Mapped I/O Signals
  235. wire IsIO; // 1: if Address is in I/O range 0x00007ff0 to 0x0007fff
  236. wire IsMemWrite;// 1: if MemWrite and not IsIO, tells us that we write to memory
  237. // and not to the IO
  238. wire [31:0] ReadMemIO; // Read from either Memory or I/O
  239.  
  240. //////////////////////////////////////////////////////////////////////////////////
  241. // The Main Part of the MIPS processor
  242.  
  243. ////////////////////////////////////
  244. // The Program Counter
  245. always @ ( posedge CLK, posedge RESET )
  246. if (RESET == 1'b1) PC <= 32'h00002FFC; // default program counter
  247. else PC <= PCbar; // Copy next value to present
  248.  
  249. // Calculation of the next PC value
  250. assign PCPlus4 = PC + 4; // By default the PC increments by 4
  251. assign PCBranch = PCPlus4 + {SignImm[29:0],2'b00}; // The branch address see Page 373, Fig 7.10
  252. assign PCCalc = PCSrc ? PCBranch : PCPlus4; // Multiplexer selects Branch or only +4
  253. assign PCJump = {PCPlus4[31:28], Instr[25:0], 2'b00}; // The Jump value
  254. assign PCbar = Jump ? PCJump : PCCalc; // Multiplexer selects Jump or Normal
  255.  
  256. /////////////////////////////////////
  257. // Instantiate the Instruction Memory
  258. InstructionMemory i_imem (
  259. .A(PC[7:2]),
  260. .RD(Instr)
  261. );
  262.  
  263. // Sign extension, replicate the MSB of the Immediate value
  264. assign SignImm = {{16{Instr[15]}},Instr[15:0]};
  265.  
  266. // Determine the Write Back address for the Register File
  267. assign WriteReg = RegDst ? Instr[15:11] : Instr[20:16];
  268.  
  269. ////////////////////////////////////
  270. // Instantiate the Register File
  271. RegisterFile i_regf (
  272. .A1(Instr[25:21]), // Address for First Register
  273. .A2(Instr[20:16]), // Address for Second Register
  274. .A3(WriteReg), // Address for Write Back
  275. .RD1(SrcA), // First output directly connected to ALU
  276. .RD2(WriteData), // Second output
  277. .WD3(Result), // Output of ALU or Data Memory
  278. .WE3(RegWrite), // From the control unit
  279. .CLK(CLK) // System Clock (10 MHz)
  280. );
  281.  
  282.  
  283. ////////////////////////////////////
  284. // ALU: first determine the inputs, and then instantiate the ALU
  285. assign SrcB = ALUSrc ? SignImm : WriteData ; // ALU input is either immediate or from register
  286.  
  287. ALU i_alu (
  288. .a(SrcA),
  289. .b(SrcB),
  290. .aluop(ALUControl[3:0]),
  291. .result(ALUResult),
  292. .zero(Zero)
  293. );
  294.  
  295. // Generate the PCSrc signal that tells to take the branch
  296. assign PCSrc = Branch & Zero; // simple AND
  297.  
  298. ////////////////////////////////////
  299. // Instantiate the Data Memory
  300. DataMemory i_dmem (
  301. .CLK(CLK), // Clock signal rising edge
  302. .A(ALUResult[7:2]), // Address for 64 locations
  303. .WE(IsMemWrite), // Write Enable 1: Write 0: no write
  304. .WD(WriteData), // 32-bit data in
  305. .RD(ReadData)
  306. );
  307.  
  308. // Memory Mapped I/O
  309. assign IsIO = (ALUResult[31:4] == 28'h00007ff) ? 1 : 0; // 1: when datamemory address
  310. // falls into I/O address range
  311. // TODO Part 1
  312. assign IsMemWrite = MemWrite & ~IsIO; // Is 1 when there is a SW instruction on DataMem address
  313. assign IOWriteData = WriteData; // This line is connected directly to WriteData
  314. assign IOAddr = ALUResult[3:0]; // The LSB 4 bits of the Address is assigned to IOAddr
  315. assign IOWriteEn = MemWrite & IsIO; // Is 1 when there is a SW instruction on IO address
  316.  
  317.  
  318. assign ReadMemIO = IsIO ? IOReadData : ReadData; // Mux selects memory or I/O
  319. // Select either the Data Memory (or IO) output or the ALU Result
  320. assign Result = MemtoReg ? ReadMemIO : ALUResult; // Slightly modified to include above
  321.  
  322. ////////////////////////////////////
  323. // The Control Unit
  324. ControlUnit i_cont (
  325. .Op(Instr[31:26]),
  326. .Funct(Instr[5:0]),
  327. .Jump(Jump),
  328. .MemtoReg(MemtoReg),
  329. .MemWrite(MemWrite),
  330. .Branch(Branch),
  331. .ALUControl(ALUControl),
  332. .ALUSrc(ALUSrc),
  333. .RegDst(RegDst),
  334. .RegWrite(RegWrite)
  335. );
  336.  
  337.  
  338. endmodule*/
  339.  
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