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Alavins

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Feb 21st, 2024
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VHDL 1.34 KB | None | 0 0
  1. LIBRARY ieee;
  2. USE ieee.std_logic_1164.ALL;
  3.  
  4. -- Uncomment the following library declaration if using
  5. -- arithmetic functions with Signed or Unsigned values
  6. --USE ieee.numeric_std.ALL;
  7.  
  8. ENTITY testMIAU IS
  9. END testMIAU;
  10.  
  11. ARCHITECTURE behavior OF testMIAU IS
  12.  
  13.     -- Component Declaration for the Unit Under Test (UUT)
  14.  
  15.     COMPONENT miau
  16.     PORT(
  17.          b1 : IN  bit;
  18.          b2 : IN  bit;
  19.          c1 : OUT  bit;
  20.          s1 : OUT  bit
  21.         );
  22.     END COMPONENT;
  23.    
  24.  
  25.    --Inputs
  26.    signal b1 : bit := '0';
  27.    signal b2 : bit := '0';
  28.  
  29.     --Outputs
  30.    signal c1 : bit;
  31.    signal s1 : bit;
  32.    -- No clocks detected in port list. Replace <clock> below with
  33.    -- appropriate port name
  34.  
  35.  
  36.  
  37. BEGIN
  38.  
  39.     -- Instantiate the Unit Under Test (UUT)
  40.    uut: miau PORT MAP (
  41.           b1 => b1,
  42.           b2 => b2,
  43.           c1 => c1,
  44.           s1 => s1
  45.         );
  46.  
  47.    -- Stimulus process
  48.    stim_proc: process
  49.    begin       
  50.       -- hold reset state for 100 ns.  
  51.         wait for 100 ns;   
  52.         b1 <= '0';
  53.         wait for 100 ns;
  54.         b2 <= '0';
  55.        
  56.         wait for 100 ns;   
  57.         b1 <= '1';
  58.         wait for 100 ns;
  59.         b2 <= '0';
  60.        
  61.         wait for 100 ns;   
  62.         b1 <= '0';
  63.         wait for 100 ns;
  64.         b2 <= '1';
  65.        
  66.         wait for 100 ns;   
  67.         b1 <= '1';
  68.         wait for 100 ns;
  69.         b2 <= '1';
  70.  
  71.       -- insert stimulus here
  72.  
  73.       wait;
  74.    end process;
  75.  
  76. END;
Tags: VHDL
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