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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity zadatakA is
- Port ( iCLK : in std_logic;
- iRST : in std_logic;
- iEN : in std_logic;
- iDEC : in std_logic_vector(2 downto 0);
- oGREAT : out std_logic;
- oCNTP : out std_logic_vector(3 downto 0);
- oCNTN : out std_logic_vector(3 downto 0)
- );
- end entity;
- architecture Behavioral of zadatakA is
- signal sDEC : std_logic_vector(7 downto 0);
- signal sREG : std_logic_vector(7 downto 0);
- signal sSHIFT : std_logic_vector(7 downto 0);
- signal sENP : std_logic;
- signal sENN : std_logic;
- signal sCNTP : std_logic_vector(3 downto 0);
- signal sCNTN : std_logic_vector(3 downto 0);
- begin
- --dekoder
- sDEC <= "00000001" when iDEC = 0 else
- "00000010" when iDEC = 1 else
- "00000100" when iDEC = 2 else
- "00001000" when iDEC = 3 else
- "00010000" when iDEC = 4 else
- "00100000" when iDEC = 5 else
- "01000000" when iDEC = 6 else
- "10000000";
- --registar
- process(iCLK, iRST)begin
- if(iRST = '1')then
- sREG <= "00000000";
- elsif(rising_edge(iCLK))then
- if(iEN = '1')then
- sREG <= sDEC;
- end if;
- end if;
- end process;
- --pomerac
- sSHIFT <= sREG(7) & sREG(7) & sREG(7 downto 2);
- --komparator
- oGREAT <= '1' when sSHIFT > 3 else '0';
- --parnost
- sENP <= '1' when sREG(0) = '0' else '0';
- sENN <= not(sENP);
- --brojac parnih
- process(iCLK, iRST)begin
- if(iRST = '1')then
- sCNTP <= (others => '0');
- elsif(rising_edge(iCLK))then
- if(sENP = '1')then
- sCNTP <= sCNTP + 1;
- end if;
- end if;
- end process;
- --brojac neparnih
- process(iCLK, iRST)begin
- if(iRST = '1')then
- sCNTN <= (others => '0');
- elsif(rising_edge(iCLK))then
- if(sENN = '1')then
- sCNTN <= sCNTN + 1;
- end if;
- end if;
- end process;
- oCNTP <= sCNTP;
- oCNTN <= sCNTN;
- end Behavioral;
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