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madegoff

blatt1_2aufgabe

May 13th, 2024
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VHDL 2.95 KB | None | 0 0
  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4.  
  5. library work;
  6. use work.ArmTypes.INSTRUCTION_ID_WIDTH;
  7. use work.ArmTypes.VCR_RESET;
  8.  
  9. entity ArmInstructionAddressRegister is
  10.     port(
  11.         IAR_CLK     : in std_logic;
  12.         IAR_RST     : in std_logic;
  13.         IAR_INC     : in std_logic;
  14.         IAR_LOAD    : in std_logic;
  15.         IAR_REVOKE  : in std_logic;
  16.         IAR_UPDATE_HB   : in std_logic;
  17. --------------------------------------------------------------------------------
  18. --  INSTRUCTION_ID_WIDTH  ist ein globaler Konfigurationsparameter
  19. --  zur Einstellung der Breite der Instruktions-IDs und damit der Tiefe
  20. --  der verteilten Puffer. Eine Breite von 3 Bit genuegt fuer die
  21. --  fuenfstufige Pipeline definitiv.
  22. --------------------------------------------------------------------------------
  23.         IAR_HISTORY_ID  : in std_logic_vector(INSTRUCTION_ID_WIDTH-1 downto 0);
  24.         IAR_ADDR_IN     : in std_logic_vector(31 downto 2);
  25.         IAR_ADDR_OUT    : out std_logic_vector(31 downto 2);
  26.         IAR_NEXT_ADDR_OUT : out std_logic_vector(31 downto 2)
  27.         );
  28.    
  29. end entity ArmInstructionAddressRegister;
  30.  
  31. architecture behave of ArmInstructionAddressRegister is
  32.  
  33.     component ArmRamBuffer
  34.     generic(
  35.         ARB_ADDR_WIDTH : natural range 1 to 4 := 3;
  36.         ARB_DATA_WIDTH : natural range 1 to 64 := 32
  37.            );
  38.     port(
  39.         ARB_CLK     : in std_logic;
  40.         ARB_WRITE_EN    : in std_logic;
  41.         ARB_ADDR    : in std_logic_vector(ARB_ADDR_WIDTH-1 downto 0);
  42.         ARB_DATA_IN : in std_logic_vector(ARB_DATA_WIDTH-1 downto 0);          
  43.         ARB_DATA_OUT    : out std_logic_vector(ARB_DATA_WIDTH-1 downto 0)
  44.         );
  45.     end component ArmRamBuffer;
  46.  
  47. signal mux1_out : std_logic_vector(31 downto 2) := (others => '0');
  48. signal mux2_out : std_logic_vector(31 downto 2) := (others => '0');
  49. signal register_out : std_logic_vector(31 downto 2);
  50. signal buffer_out : std_logic_vector(31 downto 2) := (others => '0');
  51.  
  52. begin
  53.  
  54.     reg : process(IAR_CLK) is
  55.     begin
  56.         if (rising_edge(IAR_CLK)) then
  57.            if IAR_RST = '1' then
  58.                register_out <= (others => '0');
  59.            else
  60.                register_out <= mux2_out;
  61.            end if;
  62.         end if;
  63.     end process reg;
  64.    
  65.     with IAR_INC select --erster MUX
  66.        mux1_out <= std_logic_vector(4 + unsigned(register_out)) when '1',
  67.                    register_out when others;
  68.                      
  69.     with IAR_LOAD select --zweiter MUX
  70.        mux2_out <= IAR_ADDR_IN when '1',
  71.                    mux1_out when others;
  72.                      
  73.     with IAR_REVOKE select --dritter MUX
  74.        IAR_NEXT_ADDR_OUT <= buffer_out when '1',
  75.                             std_logic_vector(4 + unsigned(register_out)) when others;
  76.        
  77.     IAR_ADDR_OUT <= register_out;
  78.  
  79.     IAR_HISTORY_BUFFER: ArmRamBuffer
  80.     generic map(
  81.             ARB_ADDR_WIDTH => INSTRUCTION_ID_WIDTH,
  82.             ARB_DATA_WIDTH => 30
  83.         )
  84.     port map(
  85.         ARB_CLK     => IAR_CLK,
  86.         ARB_WRITE_EN    => IAR_UPDATE_HB,
  87.         ARB_ADDR    => IAR_HISTORY_ID,
  88.         ARB_DATA_IN => register_out,
  89.         ARB_DATA_OUT    => buffer_out
  90.     );
  91.  
  92. end architecture behave;
  93.  
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