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vedic_div32.syr.a10641396169c7

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May 6th, 2015
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  1. Release 14.4 - xst P.49d (lin64)
  2. Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
  3. -->
  4. Parameter TMPDIR set to xst/projnav.tmp
  5.  
  6.  
  7. Total REAL time to Xst completion: 0.00 secs
  8. Total CPU time to Xst completion: 0.07 secs
  9.  
  10. -->
  11. Parameter xsthdpdir set to xst
  12.  
  13.  
  14. Total REAL time to Xst completion: 0.00 secs
  15. Total CPU time to Xst completion: 0.07 secs
  16.  
  17. -->
  18. Reading design: vedic_div32.prj
  19.  
  20. TABLE OF CONTENTS
  21. 1) Synthesis Options Summary
  22. 2) HDL Compilation
  23. 3) Design Hierarchy Analysis
  24. 4) HDL Analysis
  25. 5) HDL Synthesis
  26. 5.1) HDL Synthesis Report
  27. 6) Advanced HDL Synthesis
  28. 6.1) Advanced HDL Synthesis Report
  29. 7) Low Level Synthesis
  30. 8) Partition Report
  31. 9) Final Report
  32. 9.1) Device utilization summary
  33. 9.2) Partition Resource Summary
  34. 9.3) TIMING REPORT
  35.  
  36.  
  37. =========================================================================
  38. * Synthesis Options Summary *
  39. =========================================================================
  40. ---- Source Parameters
  41. Input File Name : "vedic_div32.prj"
  42. Input Format : mixed
  43. Ignore Synthesis Constraint File : NO
  44.  
  45. ---- Target Parameters
  46. Output File Name : "vedic_div32"
  47. Output Format : NGC
  48. Target Device : xc5vlx50t-1-ff1136
  49.  
  50. ---- Source Options
  51. Top Module Name : vedic_div32
  52. Automatic FSM Extraction : YES
  53. FSM Encoding Algorithm : Auto
  54. Safe Implementation : No
  55. FSM Style : LUT
  56. RAM Extraction : Yes
  57. RAM Style : Auto
  58. ROM Extraction : Yes
  59. Mux Style : Auto
  60. Decoder Extraction : YES
  61. Priority Encoder Extraction : Yes
  62. Shift Register Extraction : YES
  63. Logical Shifter Extraction : YES
  64. XOR Collapsing : YES
  65. ROM Style : Auto
  66. Mux Extraction : Yes
  67. Resource Sharing : YES
  68. Asynchronous To Synchronous : NO
  69. Use DSP Block : Auto
  70. Automatic Register Balancing : No
  71.  
  72. ---- Target Options
  73. LUT Combining : Off
  74. Reduce Control Sets : Off
  75. Add IO Buffers : YES
  76. Global Maximum Fanout : 100000
  77. Add Generic Clock Buffer(BUFG) : 32
  78. Register Duplication : YES
  79. Slice Packing : YES
  80. Optimize Instantiated Primitives : NO
  81. Use Clock Enable : Auto
  82. Use Synchronous Set : Auto
  83. Use Synchronous Reset : Auto
  84. Pack IO Registers into IOBs : Auto
  85. Equivalent register Removal : YES
  86.  
  87. ---- General Options
  88. Optimization Goal : Speed
  89. Optimization Effort : 1
  90. Power Reduction : NO
  91. Keep Hierarchy : No
  92. Netlist Hierarchy : As_Optimized
  93. RTL Output : Yes
  94. Global Optimization : AllClockNets
  95. Read Cores : YES
  96. Write Timing Constraints : NO
  97. Cross Clock Analysis : NO
  98. Hierarchy Separator : /
  99. Bus Delimiter : <>
  100. Case Specifier : Maintain
  101. Slice Utilization Ratio : 100
  102. BRAM Utilization Ratio : 100
  103. DSP48 Utilization Ratio : 100
  104. Verilog 2001 : YES
  105. Auto BRAM Packing : NO
  106. Slice Utilization Ratio Delta : 5
  107.  
  108. =========================================================================
  109.  
  110.  
  111. =========================================================================
  112. * HDL Compilation *
  113. =========================================================================
  114. Compiling vhdl file "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" in Library work.
  115. Architecture rtl of Entity vedic_div32 is up to date.
  116.  
  117. =========================================================================
  118. * Design Hierarchy Analysis *
  119. =========================================================================
  120. Analyzing hierarchy for entity <vedic_div32> in library <work> (architecture <rtl>).
  121.  
  122.  
  123. =========================================================================
  124. * HDL Analysis *
  125. =========================================================================
  126. Analyzing Entity <vedic_div32> in library <work> (Architecture <rtl>).
  127. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 31-bit wide.
  128. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 1-bit wide.
  129. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 30-bit wide.
  130. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 2-bit wide.
  131. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 29-bit wide.
  132. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 3-bit wide.
  133. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 28-bit wide.
  134. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 4-bit wide.
  135. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 27-bit wide.
  136. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 5-bit wide.
  137. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 26-bit wide.
  138. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 6-bit wide.
  139. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 25-bit wide.
  140. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 7-bit wide.
  141. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 24-bit wide.
  142. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 8-bit wide.
  143. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 23-bit wide.
  144. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 9-bit wide.
  145. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 22-bit wide.
  146. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 10-bit wide.
  147. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 21-bit wide.
  148. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 11-bit wide.
  149. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 20-bit wide.
  150. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 12-bit wide.
  151. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 19-bit wide.
  152. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 13-bit wide.
  153. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 18-bit wide.
  154. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 14-bit wide.
  155. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 17-bit wide.
  156. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 15-bit wide.
  157. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 16-bit wide.
  158. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 16-bit wide.
  159. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 15-bit wide.
  160. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 17-bit wide.
  161. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 14-bit wide.
  162. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 18-bit wide.
  163. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 13-bit wide.
  164. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 19-bit wide.
  165. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 12-bit wide.
  166. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 20-bit wide.
  167. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 11-bit wide.
  168. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 21-bit wide.
  169. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 10-bit wide.
  170. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 22-bit wide.
  171. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 9-bit wide.
  172. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 23-bit wide.
  173. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 8-bit wide.
  174. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 24-bit wide.
  175. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 7-bit wide.
  176. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 25-bit wide.
  177. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 6-bit wide.
  178. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 26-bit wide.
  179. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 5-bit wide.
  180. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 27-bit wide.
  181. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 4-bit wide.
  182. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 28-bit wide.
  183. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 3-bit wide.
  184. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 29-bit wide.
  185. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 2-bit wide.
  186. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 30-bit wide.
  187. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 66: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 1-bit wide.
  188. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 70: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 31-bit wide.
  189. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 105: Width mismatch. <v_reg.quo_reg> has a width of 32 bits but assigned expression is 31-bit wide.
  190. WARNING:Xst:1610 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 175: Width mismatch. <i_re> has a width of 32 bits but assigned expression is 36-bit wide.
  191. Entity <vedic_div32> analyzed. Unit <vedic_div32> generated.
  192.  
  193.  
  194. =========================================================================
  195. * HDL Synthesis *
  196. =========================================================================
  197.  
  198. Performing bidirectional port resolution...
  199.  
  200. Synthesizing Unit <vedic_div32>.
  201. Related source file is "/home/calros/enshu3-vedicdivider/vedic_div32.vhd".
  202. WARNING:Xst:653 - Signal <init_reg.quo> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
  203. Found finite state machine <FSM_0> for signal <state>.
  204. -----------------------------------------------------------------------
  205. | States | 4 |
  206. | Transitions | 9 |
  207. | Inputs | 3 |
  208. | Outputs | 3 |
  209. | Clock | mclk1 (rising_edge) |
  210. | Reset | state$and0000 (positive) |
  211. | Reset type | synchronous |
  212. | Reset State | fin_state |
  213. | Power Up State | init_state |
  214. | Encoding | automatic |
  215. | Implementation | LUT |
  216. -----------------------------------------------------------------------
  217. WARNING:Xst:737 - Found 5-bit latch for signal <shift_val>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  218. WARNING:Xst:737 - Found 36-bit latch for signal <init_reg.re_reg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  219. WARNING:Xst:737 - Found 31-bit latch for signal <b_n>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  220. WARNING:Xst:737 - Found 32-bit latch for signal <init_reg.quo_reg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  221. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 181: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  222. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 181: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  223. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 181: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  224. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 181: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  225. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 181: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  226. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 181: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  227. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 181: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  228. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 181: The result of a 34x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  229. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 197: The result of a 32x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  230. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 197: The result of a 32x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  231. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 197: The result of a 32x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  232. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 197: The result of a 32x2-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  233. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 108: The result of a 33x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  234. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 109: The result of a 33x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  235. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 181: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  236. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 181: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  237. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 181: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  238. Found 34x4-bit multiplier for signal <$mult0000> created at line 181.
  239. Found 34x5-bit multiplier for signal <$mult0001> created at line 181.
  240. Found 34x5-bit multiplier for signal <$mult0002> created at line 181.
  241. Found 34x5-bit multiplier for signal <$mult0003> created at line 181.
  242. Found 31-bit shifter logical left for signal <b_n$shift0000> created at line 64.
  243. Found 5-bit register for signal <i>.
  244. Found 5-bit subtractor for signal <i$addsub0000> created at line 135.
  245. Found 32-bit register for signal <i_quo>.
  246. Found 32-bit register for signal <i_re>.
  247. Found 36-bit shifter arithmetic right for signal <i_re$shift0001> created at line 175.
  248. Found 17-bit shifter logical left for signal <init_reg.re_reg$shift0047> created at line 70.
  249. Found 18-bit shifter logical left for signal <init_reg.re_reg$shift0048> created at line 70.
  250. Found 19-bit shifter logical left for signal <init_reg.re_reg$shift0049> created at line 70.
  251. Found 20-bit shifter logical left for signal <init_reg.re_reg$shift0050> created at line 70.
  252. Found 21-bit shifter logical left for signal <init_reg.re_reg$shift0051> created at line 70.
  253. Found 22-bit shifter logical left for signal <init_reg.re_reg$shift0052> created at line 70.
  254. Found 23-bit shifter logical left for signal <init_reg.re_reg$shift0053> created at line 70.
  255. Found 24-bit shifter logical left for signal <init_reg.re_reg$shift0054> created at line 70.
  256. Found 25-bit shifter logical left for signal <init_reg.re_reg$shift0055> created at line 70.
  257. Found 26-bit shifter logical left for signal <init_reg.re_reg$shift0056> created at line 70.
  258. Found 27-bit shifter logical left for signal <init_reg.re_reg$shift0057> created at line 70.
  259. Found 28-bit shifter logical left for signal <init_reg.re_reg$shift0058> created at line 70.
  260. Found 29-bit shifter logical left for signal <init_reg.re_reg$shift0059> created at line 70.
  261. Found 30-bit shifter logical left for signal <init_reg.re_reg$shift0060> created at line 70.
  262. Found 31-bit shifter logical left for signal <init_reg.re_reg$shift0061> created at line 70.
  263. Found 16-bit shifter logical left for signal <init_reg.re_reg$shift0062> created at line 70.
  264. Found 15-bit shifter logical left for signal <init_reg.re_reg$shift0063> created at line 70.
  265. Found 14-bit shifter logical left for signal <init_reg.re_reg$shift0064> created at line 70.
  266. Found 13-bit shifter logical left for signal <init_reg.re_reg$shift0065> created at line 70.
  267. Found 12-bit shifter logical left for signal <init_reg.re_reg$shift0066> created at line 70.
  268. Found 11-bit shifter logical left for signal <init_reg.re_reg$shift0067> created at line 70.
  269. Found 10-bit shifter logical left for signal <init_reg.re_reg$shift0068> created at line 70.
  270. Found 9-bit shifter logical left for signal <init_reg.re_reg$shift0069> created at line 70.
  271. Found 8-bit shifter logical left for signal <init_reg.re_reg$shift0070> created at line 70.
  272. Found 7-bit shifter logical left for signal <init_reg.re_reg$shift0071> created at line 70.
  273. Found 6-bit shifter logical left for signal <init_reg.re_reg$shift0072> created at line 70.
  274. Found 5-bit shifter logical left for signal <init_reg.re_reg$shift0073> created at line 70.
  275. Found 4-bit shifter logical left for signal <init_reg.re_reg$shift0074> created at line 70.
  276. Found 3-bit shifter logical left for signal <init_reg.re_reg$shift0075> created at line 70.
  277. Found 2-bit shifter logical left for signal <init_reg.re_reg$shift0076> created at line 70.
  278. Found 1-bit shifter logical left for signal <init_reg.re_reg$shift0077> created at line 70.
  279. Found 32-bit register for signal <k_reg.quo>.
  280. Found 36-bit register for signal <k_reg.re_reg>.
  281. Found 1-bit register for signal <k_reg.re_sign>.
  282. Found 32-bit register for signal <main_reg.quo>.
  283. Found 32-bit addsub for signal <main_reg.quo$mux0000>.
  284. Found 32-bit register for signal <main_reg.quo_reg>.
  285. Found 32-bit comparator greater for signal <main_reg.quo_reg$cmp_gt0000> created at line 114.
  286. Found 32-bit subtractor for signal <main_reg.quo_reg$mux0000>.
  287. Found 1-bit register for signal <main_reg.quo_sign>.
  288. Found 36-bit register for signal <main_reg.re_reg>.
  289. Found 36-bit comparator greater for signal <main_reg.re_reg$cmp_gt0000> created at line 123.
  290. Found 1-bit xor2 for signal <main_reg.re_reg$cmp_ne0000> created at line 122.
  291. Found 36-bit addsub for signal <main_reg.re_reg$mux0000>.
  292. Found 1-bit register for signal <main_reg.re_sign>.
  293. Found 32-bit comparator greatequal for signal <quo$cmp_ge0000> created at line 197.
  294. Found 32-bit comparator greatequal for signal <quo$cmp_ge0001> created at line 197.
  295. Found 32-bit comparator greatequal for signal <quo$cmp_ge0002> created at line 197.
  296. Found 32-bit comparator greatequal for signal <quo$cmp_ge0003> created at line 197.
  297. Found 32-bit comparator greatequal for signal <quo$cmp_ge0004> created at line 197.
  298. Found 32-bit comparator greatequal for signal <quo$cmp_ge0005> created at line 197.
  299. Found 32-bit comparator greatequal for signal <quo$cmp_ge0006> created at line 197.
  300. Found 32x2-bit multiplier for signal <quo$mult0004> created at line 197.
  301. Found 32x3-bit multiplier for signal <quo$mult0005> created at line 197.
  302. Found 32x3-bit multiplier for signal <quo$mult0006> created at line 197.
  303. Found 32x3-bit multiplier for signal <quo$mult0007> created at line 197.
  304. Found 32-bit addsub for signal <quo$share0000>.
  305. Found 33x32-bit multiplier for signal <quo_tmp$mult0001> created at line 108.
  306. Found 32-bit comparator greatequal for signal <re$cmp_ge0000> created at line 181.
  307. Found 32-bit comparator greatequal for signal <re$cmp_ge0001> created at line 181.
  308. Found 32-bit comparator greatequal for signal <re$cmp_ge0002> created at line 181.
  309. Found 32-bit comparator greatequal for signal <re$cmp_ge0003> created at line 181.
  310. Found 32-bit comparator greatequal for signal <re$cmp_ge0004> created at line 181.
  311. Found 32-bit comparator greatequal for signal <re$cmp_ge0005> created at line 181.
  312. Found 32-bit comparator greatequal for signal <re$cmp_ge0006> created at line 181.
  313. Found 32-bit comparator greatequal for signal <re$cmp_ge0007> created at line 181.
  314. Found 32-bit comparator greatequal for signal <re$cmp_ge0008> created at line 181.
  315. Found 32-bit comparator greatequal for signal <re$cmp_ge0009> created at line 181.
  316. Found 32-bit comparator greatequal for signal <re$cmp_ge0010> created at line 181.
  317. Found 32-bit comparator greatequal for signal <re$cmp_ge0011> created at line 181.
  318. Found 32-bit comparator greatequal for signal <re$cmp_ge0012> created at line 181.
  319. Found 32-bit comparator greatequal for signal <re$cmp_ge0013> created at line 181.
  320. Found 33x4-bit multiplier for signal <re$mult0004> created at line 181.
  321. Found 33x4-bit multiplier for signal <re$mult0005> created at line 181.
  322. Found 33x4-bit multiplier for signal <re$mult0006> created at line 181.
  323. Found 33x3-bit multiplier for signal <re$mult0007> created at line 181.
  324. Found 33x3-bit multiplier for signal <re$mult0008> created at line 181.
  325. Found 33x4-bit multiplier for signal <re$mult0009> created at line 181.
  326. Found 33x4-bit multiplier for signal <re$mult0010> created at line 181.
  327. Found 32-bit addsub for signal <re$share0000>.
  328. Found 32-bit adder for signal <re$sub0000> created at line 181.
  329. Found 32-bit adder for signal <re$sub0001> created at line 181.
  330. Found 32-bit adder for signal <re$sub0002> created at line 181.
  331. Found 32-bit adder for signal <re$sub0003> created at line 181.
  332. Found 32-bit adder for signal <re$sub0004> created at line 181.
  333. Found 32-bit adder for signal <re$sub0005> created at line 181.
  334. Found 33x32-bit multiplier for signal <re_tmp$mult0001> created at line 109.
  335. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<30:1>> created at line 109.
  336. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<0>> created at line 109.
  337. Found 32-bit shifter logical left for signal <re_tmp$shift0000> created at line 109.
  338. Found 32-bit shifter logical right for signal <tmp_quo_reg$shift0000> created at line 93.
  339. Found 36-bit adder for signal <v_re$addsub0000> created at line 172.
  340. Found 32-bit shifter logical left for signal <v_reg.quo$shift0000> created at line 97.
  341. Summary:
  342. inferred 1 Finite State Machine(s).
  343. inferred 240 D-type flip-flop(s).
  344. inferred 13 Adder/Subtractor(s).
  345. inferred 17 Multiplier(s).
  346. inferred 23 Comparator(s).
  347. inferred 31 Multiplexer(s).
  348. inferred 36 Combinational logic shifter(s).
  349. Unit <vedic_div32> synthesized.
  350.  
  351. INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
  352.  
  353. =========================================================================
  354. HDL Synthesis Report
  355.  
  356. Macro Statistics
  357. # Multipliers : 17
  358. 32x2-bit multiplier : 1
  359. 32x3-bit multiplier : 3
  360. 33x3-bit multiplier : 2
  361. 33x32-bit multiplier : 2
  362. 33x4-bit multiplier : 5
  363. 34x4-bit multiplier : 1
  364. 34x5-bit multiplier : 3
  365. # Adders/Subtractors : 13
  366. 32-bit adder : 6
  367. 32-bit addsub : 3
  368. 32-bit subtractor : 1
  369. 36-bit adder : 1
  370. 36-bit addsub : 1
  371. 5-bit subtractor : 1
  372. # Registers : 11
  373. 1-bit register : 3
  374. 32-bit register : 5
  375. 36-bit register : 2
  376. 5-bit register : 1
  377. # Latches : 4
  378. 31-bit latch : 1
  379. 32-bit latch : 1
  380. 36-bit latch : 1
  381. 5-bit latch : 1
  382. # Comparators : 23
  383. 32-bit comparator greatequal : 21
  384. 32-bit comparator greater : 1
  385. 36-bit comparator greater : 1
  386. # Multiplexers : 31
  387. 1-bit 31-to-1 multiplexer : 1
  388. 1-bit 32-to-1 multiplexer : 30
  389. # Logic shifters : 36
  390. 1-bit shifter logical left : 1
  391. 10-bit shifter logical left : 1
  392. 11-bit shifter logical left : 1
  393. 12-bit shifter logical left : 1
  394. 13-bit shifter logical left : 1
  395. 14-bit shifter logical left : 1
  396. 15-bit shifter logical left : 1
  397. 16-bit shifter logical left : 1
  398. 17-bit shifter logical left : 1
  399. 18-bit shifter logical left : 1
  400. 19-bit shifter logical left : 1
  401. 2-bit shifter logical left : 1
  402. 20-bit shifter logical left : 1
  403. 21-bit shifter logical left : 1
  404. 22-bit shifter logical left : 1
  405. 23-bit shifter logical left : 1
  406. 24-bit shifter logical left : 1
  407. 25-bit shifter logical left : 1
  408. 26-bit shifter logical left : 1
  409. 27-bit shifter logical left : 1
  410. 28-bit shifter logical left : 1
  411. 29-bit shifter logical left : 1
  412. 3-bit shifter logical left : 1
  413. 30-bit shifter logical left : 1
  414. 31-bit shifter logical left : 2
  415. 32-bit shifter logical left : 2
  416. 32-bit shifter logical right : 1
  417. 36-bit shifter arithmetic right : 1
  418. 4-bit shifter logical left : 1
  419. 5-bit shifter logical left : 1
  420. 6-bit shifter logical left : 1
  421. 7-bit shifter logical left : 1
  422. 8-bit shifter logical left : 1
  423. 9-bit shifter logical left : 1
  424. # Xors : 1
  425. 1-bit xor2 : 1
  426.  
  427. =========================================================================
  428.  
  429. =========================================================================
  430. * Advanced HDL Synthesis *
  431. =========================================================================
  432.  
  433. Analyzing FSM <FSM_0> for best encoding.
  434. Optimizing FSM <state/FSM> on signal <state[1:2]> with sequential encoding.
  435. ------------------------
  436. State | Encoding
  437. ------------------------
  438. init_state | 00
  439. main_state | 10
  440. wait_state | 11
  441. fin_state | 01
  442. ------------------------
  443. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <31>. This FF/Latch will be trimmed during the optimization process.
  444. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <32>. This FF/Latch will be trimmed during the optimization process.
  445. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <33>. This FF/Latch will be trimmed during the optimization process.
  446. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <34>. This FF/Latch will be trimmed during the optimization process.
  447. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <35>. This FF/Latch will be trimmed during the optimization process.
  448. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <main_reg.quo_sign> has a constant value of 0 in block <vedic_div32>. This FF/Latch will be trimmed during the optimization process.
  449. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <main_reg.re_sign> has a constant value of 0 in block <vedic_div32>. This FF/Latch will be trimmed during the optimization process.
  450. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <k_reg.re_sign> has a constant value of 0 in block <vedic_div32>. This FF/Latch will be trimmed during the optimization process.
  451.  
  452. Synthesizing (advanced) Unit <vedic_div32>.
  453. The following registers are absorbed into accumulator <main_reg.quo>: 1 register on signal <main_reg.quo>.
  454. Unit <vedic_div32> synthesized (advanced).
  455.  
  456. =========================================================================
  457. Advanced HDL Synthesis Report
  458.  
  459. Macro Statistics
  460. # FSMs : 1
  461. # Multipliers : 17
  462. 32x2-bit multiplier : 1
  463. 32x3-bit multiplier : 3
  464. 33x3-bit multiplier : 2
  465. 33x32-bit multiplier : 2
  466. 33x4-bit multiplier : 5
  467. 34x4-bit multiplier : 1
  468. 34x5-bit multiplier : 3
  469. # Adders/Subtractors : 12
  470. 32-bit adder : 6
  471. 32-bit addsub : 2
  472. 32-bit subtractor : 1
  473. 36-bit adder : 1
  474. 36-bit addsub : 1
  475. 5-bit subtractor : 1
  476. # Accumulators : 1
  477. 32-bit updown loadable accumulator : 1
  478. # Registers : 208
  479. Flip-Flops : 208
  480. # Latches : 4
  481. 31-bit latch : 1
  482. 32-bit latch : 1
  483. 36-bit latch : 1
  484. 5-bit latch : 1
  485. # Comparators : 23
  486. 32-bit comparator greatequal : 21
  487. 32-bit comparator greater : 1
  488. 36-bit comparator greater : 1
  489. # Multiplexers : 31
  490. 1-bit 31-to-1 multiplexer : 1
  491. 1-bit 32-to-1 multiplexer : 30
  492. # Logic shifters : 36
  493. 1-bit shifter logical left : 1
  494. 10-bit shifter logical left : 1
  495. 11-bit shifter logical left : 1
  496. 12-bit shifter logical left : 1
  497. 13-bit shifter logical left : 1
  498. 14-bit shifter logical left : 1
  499. 15-bit shifter logical left : 1
  500. 16-bit shifter logical left : 1
  501. 17-bit shifter logical left : 1
  502. 18-bit shifter logical left : 1
  503. 19-bit shifter logical left : 1
  504. 2-bit shifter logical left : 1
  505. 20-bit shifter logical left : 1
  506. 21-bit shifter logical left : 1
  507. 22-bit shifter logical left : 1
  508. 23-bit shifter logical left : 1
  509. 24-bit shifter logical left : 1
  510. 25-bit shifter logical left : 1
  511. 26-bit shifter logical left : 1
  512. 27-bit shifter logical left : 1
  513. 28-bit shifter logical left : 1
  514. 29-bit shifter logical left : 1
  515. 3-bit shifter logical left : 1
  516. 30-bit shifter logical left : 1
  517. 31-bit shifter logical left : 2
  518. 32-bit shifter logical left : 2
  519. 32-bit shifter logical right : 1
  520. 36-bit shifter arithmetic right : 1
  521. 4-bit shifter logical left : 1
  522. 5-bit shifter logical left : 1
  523. 6-bit shifter logical left : 1
  524. 7-bit shifter logical left : 1
  525. 8-bit shifter logical left : 1
  526. 9-bit shifter logical left : 1
  527. # Xors : 1
  528. 1-bit xor2 : 1
  529.  
  530. =========================================================================
  531.  
  532. =========================================================================
  533. * Low Level Synthesis *
  534. =========================================================================
  535. WARNING:Xst:1293 - FF/Latch <main_reg.quo_sign> has a constant value of 0 in block <vedic_div32>. This FF/Latch will be trimmed during the optimization process.
  536. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <main_reg.re_sign> has a constant value of 0 in block <vedic_div32>. This FF/Latch will be trimmed during the optimization process.
  537. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <k_reg.re_sign> has a constant value of 0 in block <vedic_div32>. This FF/Latch will be trimmed during the optimization process.
  538. INFO:Xst:2261 - The FF/Latch <35> in Unit <LPM_LATCH_7> is equivalent to the following 4 FFs/Latches, which will be removed : <34> <33> <32> <31>
  539. WARNING:Xst:1293 - FF/Latch <35> has a constant value of 0 in block <LPM_LATCH_7>. This FF/Latch will be trimmed during the optimization process.
  540. WARNING:Xst:2677 - Node <Mmult_quo_tmp_mult00013> of sequential type is unconnected in block <vedic_div32>.
  541. WARNING:Xst:2677 - Node <Mmult_re_tmp_mult00013> of sequential type is unconnected in block <vedic_div32>.
  542.  
  543. Optimizing unit <vedic_div32> ...
  544.  
  545. Mapping all equations...
  546. Building and optimizing final netlist ...
  547. Found area constraint ratio of 100 (+ 5) on block vedic_div32, actual ratio is 15.
  548.  
  549. Final Macro Processing ...
  550.  
  551. =========================================================================
  552. Final Register Report
  553.  
  554. Macro Statistics
  555. # Registers : 239
  556. Flip-Flops : 239
  557.  
  558. =========================================================================
  559.  
  560. =========================================================================
  561. * Partition Report *
  562. =========================================================================
  563.  
  564. Partition Implementation Status
  565. -------------------------------
  566.  
  567. No Partitions were found in this design.
  568.  
  569. -------------------------------
  570.  
  571. =========================================================================
  572. * Final Report *
  573. =========================================================================
  574. Final Results
  575. RTL Top Level Output File Name : vedic_div32.ngr
  576. Top Level Output File Name : vedic_div32
  577. Output Format : NGC
  578. Optimization Goal : Speed
  579. Keep Hierarchy : No
  580.  
  581. Design Statistics
  582. # IOs : 130
  583.  
  584. Cell Usage :
  585. # BELS : 5689
  586. # GND : 1
  587. # INV : 192
  588. # LUT1 : 3
  589. # LUT2 : 644
  590. # LUT3 : 178
  591. # LUT4 : 948
  592. # LUT5 : 289
  593. # LUT6 : 1121
  594. # MUXCY : 1220
  595. # MUXF7 : 193
  596. # VCC : 1
  597. # XORCY : 899
  598. # FlipFlops/Latches : 338
  599. # FD : 151
  600. # FDE : 68
  601. # FDR : 1
  602. # FDS : 19
  603. # LDCP : 99
  604. # Clock Buffers : 2
  605. # BUFG : 1
  606. # BUFGP : 1
  607. # IO Buffers : 129
  608. # IBUF : 65
  609. # OBUF : 64
  610. # DSPs : 6
  611. # DSP48E : 6
  612. =========================================================================
  613.  
  614. Device utilization summary:
  615. ---------------------------
  616.  
  617. Selected Device : 5vlx50tff1136-1
  618.  
  619.  
  620. Slice Logic Utilization:
  621. Number of Slice Registers: 338 out of 28800 1%
  622. Number of Slice LUTs: 3375 out of 28800 11%
  623. Number used as Logic: 3375 out of 28800 11%
  624.  
  625. Slice Logic Distribution:
  626. Number of LUT Flip Flop pairs used: 3433
  627. Number with an unused Flip Flop: 3095 out of 3433 90%
  628. Number with an unused LUT: 58 out of 3433 1%
  629. Number of fully used LUT-FF pairs: 280 out of 3433 8%
  630. Number of unique control sets: 108
  631.  
  632. IO Utilization:
  633. Number of IOs: 130
  634. Number of bonded IOBs: 130 out of 480 27%
  635.  
  636. Specific Feature Utilization:
  637. Number of BUFG/BUFGCTRLs: 2 out of 32 6%
  638. Number of DSP48Es: 6 out of 48 12%
  639.  
  640. ---------------------------
  641. Partition Resource Summary:
  642. ---------------------------
  643.  
  644. No Partitions were found in this design.
  645.  
  646. ---------------------------
  647.  
  648.  
  649. =========================================================================
  650. TIMING REPORT
  651.  
  652. NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
  653. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
  654. GENERATED AFTER PLACE-and-ROUTE.
  655.  
  656. Clock Information:
  657. ------------------
  658. -----------------------------------+------------------------+-------+
  659. Clock Signal | Clock buffer(FF name) | Load |
  660. -----------------------------------+------------------------+-------+
  661. mclk1 | BUFGP | 239 |
  662. divisor<0> | IBUF+BUFG | 99 |
  663. -----------------------------------+------------------------+-------+
  664.  
  665. Asynchronous Control Signals Information:
  666. ----------------------------------------
  667. -------------------------------------------------------------+--------------------------+-------+
  668. Control Signal | Buffer(FF name) | Load |
  669. -------------------------------------------------------------+--------------------------+-------+
  670. Madd_re_sub0005_lut<0>(XST_GND:G) | NONE(init_reg.quo_reg_31)| 1 |
  671. Sh1538(Sh16001:O) | NONE(b_n_1) | 1 |
  672. Sh1539(Sh15391:O) | NONE(b_n_2) | 1 |
  673. b_n_0__and0000(b_n_0__and00001:O) | NONE(b_n_0) | 1 |
  674. b_n_0__and0001(b_n_0__and00011:O) | NONE(b_n_0) | 1 |
  675. b_n_10__and0000(b_n_10__and00001:O) | NONE(b_n_10) | 1 |
  676. b_n_10__and0001(b_n_10__and00011:O) | NONE(b_n_10) | 1 |
  677. b_n_11__and0000(b_n_11__and00001:O) | NONE(b_n_11) | 1 |
  678. b_n_11__and0001(b_n_11__and00011:O) | NONE(b_n_11) | 1 |
  679. b_n_12__and0000(b_n_12__and00001:O) | NONE(b_n_12) | 1 |
  680. b_n_12__and0001(b_n_12__and00011:O) | NONE(b_n_12) | 1 |
  681. b_n_13__and0000(b_n_13__and00001:O) | NONE(b_n_13) | 1 |
  682. b_n_13__and0001(b_n_13__and00011:O) | NONE(b_n_13) | 1 |
  683. b_n_14__and0000(b_n_14__and00001:O) | NONE(b_n_14) | 1 |
  684. b_n_14__and0001(b_n_14__and00011:O) | NONE(b_n_14) | 1 |
  685. b_n_15__and0000(b_n_15__and00001:O) | NONE(b_n_15) | 1 |
  686. b_n_15__and0001(b_n_15__and00011:O) | NONE(b_n_15) | 1 |
  687. b_n_16__and0000(b_n_16__and00001:O) | NONE(b_n_16) | 1 |
  688. b_n_16__and0001(b_n_16__and00011:O) | NONE(b_n_16) | 1 |
  689. b_n_17__and0000(b_n_17__and00001:O) | NONE(b_n_17) | 1 |
  690. b_n_17__and0001(b_n_17__and00011:O) | NONE(b_n_17) | 1 |
  691. b_n_18__and0000(b_n_18__and00001:O) | NONE(b_n_18) | 1 |
  692. b_n_18__and0001(b_n_18__and00011:O) | NONE(b_n_18) | 1 |
  693. b_n_19__and0000(b_n_19__and00001:O) | NONE(b_n_19) | 1 |
  694. b_n_19__and0001(b_n_19__and00011:O) | NONE(b_n_19) | 1 |
  695. b_n_1__and0000(b_n_1__and00001:O) | NONE(b_n_1) | 1 |
  696. b_n_20__and0000(b_n_20__and00001:O) | NONE(b_n_20) | 1 |
  697. b_n_20__and0001(b_n_20__and00011:O) | NONE(b_n_20) | 1 |
  698. b_n_21__and0000(b_n_21__and00001:O) | NONE(b_n_21) | 1 |
  699. b_n_21__and0001(b_n_21__and00011:O) | NONE(b_n_21) | 1 |
  700. b_n_22__and0000(b_n_22__and00001:O) | NONE(b_n_22) | 1 |
  701. b_n_22__and0001(b_n_22__and00011:O) | NONE(b_n_22) | 1 |
  702. b_n_23__and0000(b_n_23__and00001:O) | NONE(b_n_23) | 1 |
  703. b_n_23__and0001(b_n_23__and00011:O) | NONE(b_n_23) | 1 |
  704. b_n_24__and0000(b_n_24__and00001:O) | NONE(b_n_24) | 1 |
  705. b_n_24__and0001(b_n_24__and00011:O) | NONE(b_n_24) | 1 |
  706. b_n_25__and0000(b_n_25__and00001:O) | NONE(b_n_25) | 1 |
  707. b_n_25__and0001(b_n_25__and00011:O) | NONE(b_n_25) | 1 |
  708. b_n_26__and0000(b_n_26__and00001:O) | NONE(b_n_26) | 1 |
  709. b_n_26__and0001(b_n_26__and00011:O) | NONE(b_n_26) | 1 |
  710. b_n_27__and0000(b_n_27__and00001:O) | NONE(b_n_27) | 1 |
  711. b_n_27__and0001(b_n_27__and00011:O) | NONE(b_n_27) | 1 |
  712. b_n_28__and0000(b_n_28__and00001:O) | NONE(b_n_28) | 1 |
  713. b_n_28__and0001(b_n_28__and00011:O) | NONE(b_n_28) | 1 |
  714. b_n_29__and0000(b_n_29__and00001:O) | NONE(b_n_29) | 1 |
  715. b_n_29__and0001(b_n_29__and00011:O) | NONE(b_n_29) | 1 |
  716. b_n_2__and0000(b_n_2__and00001:O) | NONE(b_n_2) | 1 |
  717. b_n_30__and0000(b_n_30__and00001:O) | NONE(b_n_30) | 1 |
  718. b_n_30__and0001(b_n_30__and00011:O) | NONE(b_n_30) | 1 |
  719. b_n_3__and0000(b_n_3__and00001:O) | NONE(b_n_3) | 1 |
  720. b_n_3__and0001(b_n_3__and00011:O) | NONE(b_n_3) | 1 |
  721. b_n_4__and0000(b_n_4__and00001:O) | NONE(b_n_4) | 1 |
  722. b_n_4__and0001(b_n_4__and00011:O) | NONE(b_n_4) | 1 |
  723. b_n_5__and0000(b_n_5__and00001:O) | NONE(b_n_5) | 1 |
  724. b_n_5__and0001(b_n_5__and00011:O) | NONE(b_n_5) | 1 |
  725. b_n_6__and0000(b_n_6__and00001:O) | NONE(b_n_6) | 1 |
  726. b_n_6__and0001(b_n_6__and00011:O) | NONE(b_n_6) | 1 |
  727. b_n_7__and0000(b_n_7__and00001:O) | NONE(b_n_7) | 1 |
  728. b_n_7__and0001(b_n_7__and00011:O) | NONE(b_n_7) | 1 |
  729. b_n_8__and0000(b_n_8__and00001:O) | NONE(b_n_8) | 1 |
  730. b_n_8__and0001(b_n_8__and00011:O) | NONE(b_n_8) | 1 |
  731. b_n_9__and0000(b_n_9__and00001:O) | NONE(b_n_9) | 1 |
  732. b_n_9__and0001(b_n_9__and00011:O) | NONE(b_n_9) | 1 |
  733. init_reg.quo_reg_0__and0000(init_reg.quo_reg_0__and00001:O) | NONE(init_reg.quo_reg_0) | 1 |
  734. init_reg.quo_reg_0__and0001(init_reg.quo_reg_0__and00011:O) | NONE(init_reg.quo_reg_0) | 1 |
  735. init_reg.quo_reg_10__and0000(init_reg.quo_reg_10__and00001:O)| NONE(init_reg.quo_reg_10)| 1 |
  736. init_reg.quo_reg_10__and0001(init_reg.quo_reg_10__and00011:O)| NONE(init_reg.quo_reg_10)| 1 |
  737. init_reg.quo_reg_11__and0000(init_reg.quo_reg_11__and00001:O)| NONE(init_reg.quo_reg_11)| 1 |
  738. init_reg.quo_reg_11__and0001(init_reg.quo_reg_11__and00011:O)| NONE(init_reg.quo_reg_11)| 1 |
  739. init_reg.quo_reg_12__and0000(init_reg.quo_reg_12__and00001:O)| NONE(init_reg.quo_reg_12)| 1 |
  740. init_reg.quo_reg_12__and0001(init_reg.quo_reg_12__and00011:O)| NONE(init_reg.quo_reg_12)| 1 |
  741. init_reg.quo_reg_13__and0000(init_reg.quo_reg_13__and00001:O)| NONE(init_reg.quo_reg_13)| 1 |
  742. init_reg.quo_reg_13__and0001(init_reg.quo_reg_13__and00011:O)| NONE(init_reg.quo_reg_13)| 1 |
  743. init_reg.quo_reg_14__and0000(init_reg.quo_reg_14__and00001:O)| NONE(init_reg.quo_reg_14)| 1 |
  744. init_reg.quo_reg_14__and0001(init_reg.quo_reg_14__and00011:O)| NONE(init_reg.quo_reg_14)| 1 |
  745. init_reg.quo_reg_15__and0000(init_reg.quo_reg_15__and00001:O)| NONE(init_reg.quo_reg_15)| 1 |
  746. init_reg.quo_reg_15__and0001(init_reg.quo_reg_15__and00011:O)| NONE(init_reg.quo_reg_15)| 1 |
  747. init_reg.quo_reg_16__and0000(init_reg.quo_reg_16__and00001:O)| NONE(init_reg.quo_reg_16)| 1 |
  748. init_reg.quo_reg_16__and0001(init_reg.quo_reg_16__and00011:O)| NONE(init_reg.quo_reg_16)| 1 |
  749. init_reg.quo_reg_17__and0000(init_reg.quo_reg_17__and00001:O)| NONE(init_reg.quo_reg_17)| 1 |
  750. init_reg.quo_reg_17__and0001(init_reg.quo_reg_17__and00011:O)| NONE(init_reg.quo_reg_17)| 1 |
  751. init_reg.quo_reg_18__and0000(init_reg.quo_reg_18__and00001:O)| NONE(init_reg.quo_reg_18)| 1 |
  752. init_reg.quo_reg_18__and0001(init_reg.quo_reg_18__and00011:O)| NONE(init_reg.quo_reg_18)| 1 |
  753. init_reg.quo_reg_19__and0000(init_reg.quo_reg_19__and00001:O)| NONE(init_reg.quo_reg_19)| 1 |
  754. init_reg.quo_reg_19__and0001(init_reg.quo_reg_19__and00011:O)| NONE(init_reg.quo_reg_19)| 1 |
  755. init_reg.quo_reg_1__and0000(init_reg.quo_reg_1__and00001:O) | NONE(init_reg.quo_reg_1) | 1 |
  756. init_reg.quo_reg_1__and0001(init_reg.quo_reg_1__and00011:O) | NONE(init_reg.quo_reg_1) | 1 |
  757. init_reg.quo_reg_20__and0000(init_reg.quo_reg_20__and00001:O)| NONE(init_reg.quo_reg_20)| 1 |
  758. init_reg.quo_reg_20__and0001(init_reg.quo_reg_20__and00011:O)| NONE(init_reg.quo_reg_20)| 1 |
  759. init_reg.quo_reg_21__and0000(init_reg.quo_reg_21__and00001:O)| NONE(init_reg.quo_reg_21)| 1 |
  760. init_reg.quo_reg_21__and0001(init_reg.quo_reg_21__and00011:O)| NONE(init_reg.quo_reg_21)| 1 |
  761. init_reg.quo_reg_22__and0000(init_reg.quo_reg_22__and00001:O)| NONE(init_reg.quo_reg_22)| 1 |
  762. init_reg.quo_reg_22__and0001(init_reg.quo_reg_22__and00011:O)| NONE(init_reg.quo_reg_22)| 1 |
  763. init_reg.quo_reg_23__and0000(init_reg.quo_reg_23__and00001:O)| NONE(init_reg.quo_reg_23)| 1 |
  764. init_reg.quo_reg_23__and0001(init_reg.quo_reg_23__and00011:O)| NONE(init_reg.quo_reg_23)| 1 |
  765. init_reg.quo_reg_24__and0000(init_reg.quo_reg_24__and00001:O)| NONE(init_reg.quo_reg_24)| 1 |
  766. init_reg.quo_reg_24__and0001(init_reg.quo_reg_24__and00011:O)| NONE(init_reg.quo_reg_24)| 1 |
  767. init_reg.quo_reg_25__and0000(init_reg.quo_reg_25__and00001:O)| NONE(init_reg.quo_reg_25)| 1 |
  768. init_reg.quo_reg_25__and0001(init_reg.quo_reg_25__and00011:O)| NONE(init_reg.quo_reg_25)| 1 |
  769. init_reg.quo_reg_26__and0000(init_reg.quo_reg_26__and00001:O)| NONE(init_reg.quo_reg_26)| 1 |
  770. init_reg.quo_reg_26__and0001(init_reg.quo_reg_26__and00011:O)| NONE(init_reg.quo_reg_26)| 1 |
  771. init_reg.quo_reg_27__and0000(init_reg.quo_reg_27__and00001:O)| NONE(init_reg.quo_reg_27)| 1 |
  772. init_reg.quo_reg_27__and0001(init_reg.quo_reg_27__and00011:O)| NONE(init_reg.quo_reg_27)| 1 |
  773. init_reg.quo_reg_28__and0000(init_reg.quo_reg_28__and00001:O)| NONE(init_reg.quo_reg_28)| 1 |
  774. init_reg.quo_reg_28__and0001(init_reg.quo_reg_28__and00011:O)| NONE(init_reg.quo_reg_28)| 1 |
  775. init_reg.quo_reg_29__and0000(init_reg.quo_reg_29__and00001:O)| NONE(init_reg.quo_reg_29)| 1 |
  776. init_reg.quo_reg_29__and0001(init_reg.quo_reg_29__and00011:O)| NONE(init_reg.quo_reg_29)| 1 |
  777. init_reg.quo_reg_2__and0000(init_reg.quo_reg_2__and00001:O) | NONE(init_reg.quo_reg_2) | 1 |
  778. init_reg.quo_reg_2__and0001(init_reg.quo_reg_2__and00011:O) | NONE(init_reg.quo_reg_2) | 1 |
  779. init_reg.quo_reg_30__and0000(init_reg.quo_reg_30__and00001:O)| NONE(init_reg.quo_reg_30)| 1 |
  780. init_reg.quo_reg_30__and0001(init_reg.quo_reg_30__and00011:O)| NONE(init_reg.quo_reg_30)| 1 |
  781. init_reg.quo_reg_3__and0000(init_reg.quo_reg_3__and00001:O) | NONE(init_reg.quo_reg_3) | 1 |
  782. init_reg.quo_reg_3__and0001(init_reg.quo_reg_3__and00011:O) | NONE(init_reg.quo_reg_3) | 1 |
  783. init_reg.quo_reg_4__and0000(init_reg.quo_reg_4__and00001:O) | NONE(init_reg.quo_reg_4) | 1 |
  784. init_reg.quo_reg_4__and0001(init_reg.quo_reg_4__and00011:O) | NONE(init_reg.quo_reg_4) | 1 |
  785. init_reg.quo_reg_5__and0000(init_reg.quo_reg_5__and00001:O) | NONE(init_reg.quo_reg_5) | 1 |
  786. init_reg.quo_reg_5__and0001(init_reg.quo_reg_5__and00011:O) | NONE(init_reg.quo_reg_5) | 1 |
  787. init_reg.quo_reg_6__and0000(init_reg.quo_reg_6__and00001:O) | NONE(init_reg.quo_reg_6) | 1 |
  788. init_reg.quo_reg_6__and0001(init_reg.quo_reg_6__and00011:O) | NONE(init_reg.quo_reg_6) | 1 |
  789. init_reg.quo_reg_7__and0000(init_reg.quo_reg_7__and00001:O) | NONE(init_reg.quo_reg_7) | 1 |
  790. init_reg.quo_reg_7__and0001(init_reg.quo_reg_7__and00011:O) | NONE(init_reg.quo_reg_7) | 1 |
  791. init_reg.quo_reg_8__and0000(init_reg.quo_reg_8__and00001:O) | NONE(init_reg.quo_reg_8) | 1 |
  792. init_reg.quo_reg_8__and0001(init_reg.quo_reg_8__and00011:O) | NONE(init_reg.quo_reg_8) | 1 |
  793. init_reg.quo_reg_9__and0000(init_reg.quo_reg_9__and00001:O) | NONE(init_reg.quo_reg_9) | 1 |
  794. init_reg.quo_reg_9__and0001(init_reg.quo_reg_9__and00011:O) | NONE(init_reg.quo_reg_9) | 1 |
  795. init_reg.re_reg_0__and0000(init_reg.re_reg_0__and00001:O) | NONE(init_reg.re_reg_0) | 1 |
  796. init_reg.re_reg_0__and0001(init_reg.re_reg_0__and00011:O) | NONE(init_reg.re_reg_0) | 1 |
  797. init_reg.re_reg_10__and0000(init_reg.re_reg_10__and00001:O) | NONE(init_reg.re_reg_10) | 1 |
  798. init_reg.re_reg_10__and0001(init_reg.re_reg_10__and00011:O) | NONE(init_reg.re_reg_10) | 1 |
  799. init_reg.re_reg_11__and0000(init_reg.re_reg_11__and00001:O) | NONE(init_reg.re_reg_11) | 1 |
  800. init_reg.re_reg_11__and0001(init_reg.re_reg_11__and00011:O) | NONE(init_reg.re_reg_11) | 1 |
  801. init_reg.re_reg_12__and0000(init_reg.re_reg_12__and00001:O) | NONE(init_reg.re_reg_12) | 1 |
  802. init_reg.re_reg_12__and0001(init_reg.re_reg_12__and00011:O) | NONE(init_reg.re_reg_12) | 1 |
  803. init_reg.re_reg_13__and0000(init_reg.re_reg_13__and00001:O) | NONE(init_reg.re_reg_13) | 1 |
  804. init_reg.re_reg_13__and0001(init_reg.re_reg_13__and00011:O) | NONE(init_reg.re_reg_13) | 1 |
  805. init_reg.re_reg_14__and0000(init_reg.re_reg_14__and00001:O) | NONE(init_reg.re_reg_14) | 1 |
  806. init_reg.re_reg_14__and0001(init_reg.re_reg_14__and00011:O) | NONE(init_reg.re_reg_14) | 1 |
  807. init_reg.re_reg_15__and0000(init_reg.re_reg_15__and00001:O) | NONE(init_reg.re_reg_15) | 1 |
  808. init_reg.re_reg_15__and0001(init_reg.re_reg_15__and00011:O) | NONE(init_reg.re_reg_15) | 1 |
  809. init_reg.re_reg_16__and0000(init_reg.re_reg_16__and00001:O) | NONE(init_reg.re_reg_16) | 1 |
  810. init_reg.re_reg_16__and0001(init_reg.re_reg_16__and00011:O) | NONE(init_reg.re_reg_16) | 1 |
  811. init_reg.re_reg_17__and0000(init_reg.re_reg_17__and00001:O) | NONE(init_reg.re_reg_17) | 1 |
  812. init_reg.re_reg_17__and0001(init_reg.re_reg_17__and00011:O) | NONE(init_reg.re_reg_17) | 1 |
  813. init_reg.re_reg_18__and0000(init_reg.re_reg_18__and00001:O) | NONE(init_reg.re_reg_18) | 1 |
  814. init_reg.re_reg_18__and0001(init_reg.re_reg_18__and00011:O) | NONE(init_reg.re_reg_18) | 1 |
  815. init_reg.re_reg_19__and0000(init_reg.re_reg_19__and00001:O) | NONE(init_reg.re_reg_19) | 1 |
  816. init_reg.re_reg_19__and0001(init_reg.re_reg_19__and00011:O) | NONE(init_reg.re_reg_19) | 1 |
  817. init_reg.re_reg_1__and0000(init_reg.re_reg_1__and00001:O) | NONE(init_reg.re_reg_1) | 1 |
  818. init_reg.re_reg_1__and0001(init_reg.re_reg_1__and00011:O) | NONE(init_reg.re_reg_1) | 1 |
  819. init_reg.re_reg_20__and0000(init_reg.re_reg_20__and00001:O) | NONE(init_reg.re_reg_20) | 1 |
  820. init_reg.re_reg_20__and0001(init_reg.re_reg_20__and00011:O) | NONE(init_reg.re_reg_20) | 1 |
  821. init_reg.re_reg_21__and0000(init_reg.re_reg_21__and00001:O) | NONE(init_reg.re_reg_21) | 1 |
  822. init_reg.re_reg_21__and0001(init_reg.re_reg_21__and00011:O) | NONE(init_reg.re_reg_21) | 1 |
  823. init_reg.re_reg_22__and0000(init_reg.re_reg_22__and00001:O) | NONE(init_reg.re_reg_22) | 1 |
  824. init_reg.re_reg_22__and0001(init_reg.re_reg_22__and00011:O) | NONE(init_reg.re_reg_22) | 1 |
  825. init_reg.re_reg_23__and0000(init_reg.re_reg_23__and00001:O) | NONE(init_reg.re_reg_23) | 1 |
  826. init_reg.re_reg_23__and0001(init_reg.re_reg_23__and00011:O) | NONE(init_reg.re_reg_23) | 1 |
  827. init_reg.re_reg_24__and0000(init_reg.re_reg_24__and00001:O) | NONE(init_reg.re_reg_24) | 1 |
  828. init_reg.re_reg_24__and0001(init_reg.re_reg_24__and00011:O) | NONE(init_reg.re_reg_24) | 1 |
  829. init_reg.re_reg_25__and0000(init_reg.re_reg_25__and00001:O) | NONE(init_reg.re_reg_25) | 1 |
  830. init_reg.re_reg_25__and0001(init_reg.re_reg_25__and00011:O) | NONE(init_reg.re_reg_25) | 1 |
  831. init_reg.re_reg_26__and0000(init_reg.re_reg_26__and00001:O) | NONE(init_reg.re_reg_26) | 1 |
  832. init_reg.re_reg_26__and0001(init_reg.re_reg_26__and00011:O) | NONE(init_reg.re_reg_26) | 1 |
  833. init_reg.re_reg_27__and0000(init_reg.re_reg_27__and00001:O) | NONE(init_reg.re_reg_27) | 1 |
  834. init_reg.re_reg_27__and0001(init_reg.re_reg_27__and00011:O) | NONE(init_reg.re_reg_27) | 1 |
  835. init_reg.re_reg_28__and0000(init_reg.re_reg_28__and00001:O) | NONE(init_reg.re_reg_28) | 1 |
  836. init_reg.re_reg_28__and0001(init_reg.re_reg_28__and00011:O) | NONE(init_reg.re_reg_28) | 1 |
  837. init_reg.re_reg_29__and0000(init_reg.re_reg_29__and00001:O) | NONE(init_reg.re_reg_29) | 1 |
  838. init_reg.re_reg_29__and0001(init_reg.re_reg_29__and00011:O) | NONE(init_reg.re_reg_29) | 1 |
  839. init_reg.re_reg_2__and0000(init_reg.re_reg_2__and00001:O) | NONE(init_reg.re_reg_2) | 1 |
  840. init_reg.re_reg_2__and0001(init_reg.re_reg_2__and00011:O) | NONE(init_reg.re_reg_2) | 1 |
  841. init_reg.re_reg_30__and0000(init_reg.re_reg_30__and00001:O) | NONE(init_reg.re_reg_30) | 1 |
  842. init_reg.re_reg_30__and0001(init_reg.re_reg_30__and00011:O) | NONE(init_reg.re_reg_30) | 1 |
  843. init_reg.re_reg_3__and0000(init_reg.re_reg_3__and00001:O) | NONE(init_reg.re_reg_3) | 1 |
  844. init_reg.re_reg_3__and0001(init_reg.re_reg_3__and00011:O) | NONE(init_reg.re_reg_3) | 1 |
  845. init_reg.re_reg_4__and0000(init_reg.re_reg_4__and00001:O) | NONE(init_reg.re_reg_4) | 1 |
  846. init_reg.re_reg_4__and0001(init_reg.re_reg_4__and00011:O) | NONE(init_reg.re_reg_4) | 1 |
  847. init_reg.re_reg_5__and0000(init_reg.re_reg_5__and00001:O) | NONE(init_reg.re_reg_5) | 1 |
  848. init_reg.re_reg_5__and0001(init_reg.re_reg_5__and00011:O) | NONE(init_reg.re_reg_5) | 1 |
  849. init_reg.re_reg_6__and0000(init_reg.re_reg_6__and00001:O) | NONE(init_reg.re_reg_6) | 1 |
  850. init_reg.re_reg_6__and0001(init_reg.re_reg_6__and00011:O) | NONE(init_reg.re_reg_6) | 1 |
  851. init_reg.re_reg_7__and0000(init_reg.re_reg_7__and00001:O) | NONE(init_reg.re_reg_7) | 1 |
  852. init_reg.re_reg_7__and0001(init_reg.re_reg_7__and00011:O) | NONE(init_reg.re_reg_7) | 1 |
  853. init_reg.re_reg_8__and0000(init_reg.re_reg_8__and00001:O) | NONE(init_reg.re_reg_8) | 1 |
  854. init_reg.re_reg_8__and0001(init_reg.re_reg_8__and00011:O) | NONE(init_reg.re_reg_8) | 1 |
  855. init_reg.re_reg_9__and0000(init_reg.re_reg_9__and00001:O) | NONE(init_reg.re_reg_9) | 1 |
  856. init_reg.re_reg_9__and0001(init_reg.re_reg_9__and00011:O) | NONE(init_reg.re_reg_9) | 1 |
  857. init_reg_re_reg_or0001(init_reg_re_reg_or00011:O) | NONE(init_reg.quo_reg_31)| 1 |
  858. shift_val_0__or0000(shift_val_0__or00001:O) | NONE(shift_val_0) | 1 |
  859. shift_val_0__or0001(shift_val_0__or00011:O) | NONE(shift_val_0) | 1 |
  860. shift_val_1__and0000(shift_val_1__and00001:O) | NONE(shift_val_1) | 1 |
  861. shift_val_1__or0000(shift_val_1__or00001:O) | NONE(shift_val_1) | 1 |
  862. shift_val_2__and0000(shift_val_2__and00001:O) | NONE(shift_val_2) | 1 |
  863. shift_val_2__or0000(shift_val_2__or00001:O) | NONE(shift_val_2) | 1 |
  864. shift_val_3__and0000(shift_val_3__and00001:O) | NONE(shift_val_3) | 1 |
  865. shift_val_3__or0000(shift_val_3__or00001:O) | NONE(shift_val_3) | 1 |
  866. shift_val_4__and0000(shift_val_4__and00001:O) | NONE(shift_val_4) | 1 |
  867. shift_val_4__or0000(shift_val_4__or00001:O) | NONE(shift_val_4) | 1 |
  868. -------------------------------------------------------------+--------------------------+-------+
  869.  
  870. Timing Summary:
  871. ---------------
  872. Speed Grade: -1
  873.  
  874. Minimum period: 17.930ns (Maximum Frequency: 55.774MHz)
  875. Minimum input arrival time before clock: 8.017ns
  876. Maximum output required time after clock: 12.422ns
  877. Maximum combinational path delay: 15.842ns
  878.  
  879. Timing Detail:
  880. --------------
  881. All values displayed in nanoseconds (ns)
  882.  
  883. =========================================================================
  884. Timing constraint: Default period analysis for Clock 'mclk1'
  885. Clock period: 17.930ns (frequency: 55.774MHz)
  886. Total number of paths / destination ports: 687092582852 / 327
  887. -------------------------------------------------------------------------
  888. Delay: 17.930ns (Levels of Logic = 54)
  889. Source: state_FSM_FFd1 (FF)
  890. Destination: main_reg.re_reg_35 (FF)
  891. Source Clock: mclk1 rising
  892. Destination Clock: mclk1 rising
  893.  
  894. Data Path: state_FSM_FFd1 to main_reg.re_reg_35
  895. Gate Net
  896. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  897. ---------------------------------------- ------------
  898. FDR:C->Q 321 0.471 0.757 state_FSM_FFd1 (state_FSM_FFd1)
  899. LUT4:I2->O 5 0.094 0.598 reg_quo_reg<2>1 (reg_quo_reg<2>)
  900. LUT4:I2->O 1 0.094 0.710 Sh150527 (Sh150527)
  901. LUT4:I1->O 2 0.094 0.581 Sh150597 (Sh150597)
  902. LUT6:I4->O 1 0.094 0.000 Sh1505160_G (N1192)
  903. MUXF7:I1->O 10 0.254 0.385 Sh1505160 (Sh1505)
  904. DSP48E:B0->PCOUT46 1 3.832 0.000 Mmult_re_tmp_mult0001 (Mmult_re_tmp_mult0001_PCOUT_to_Mmult_re_tmp_mult00011_PCIN_46)
  905. DSP48E:PCIN46->PCOUT35 1 2.013 0.000 Mmult_re_tmp_mult00011 (Mmult_re_tmp_mult00011_PCOUT_to_Mmult_re_tmp_mult00012_PCIN_35)
  906. DSP48E:PCIN35->P1 6 1.816 0.816 Mmult_re_tmp_mult00012 (re_tmp_mult0001<18>)
  907. LUT6:I2->O 4 0.094 0.989 Sh17471 (Sh1747)
  908. LUT6:I1->O 1 0.094 0.000 Sh1815_F (N1255)
  909. MUXF7:I0->O 3 0.251 0.800 Sh1815 (Sh1815)
  910. LUT4:I0->O 0 0.094 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_lutdi12 (Mcompar_main_reg.re_reg_cmp_gt0000_lutdi12)
  911. MUXCY:DI->O 1 0.362 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_cy<12> (Mcompar_main_reg.re_reg_cmp_gt0000_cy<12>)
  912. MUXCY:CI->O 1 0.026 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_cy<13> (Mcompar_main_reg.re_reg_cmp_gt0000_cy<13>)
  913. MUXCY:CI->O 1 0.026 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_cy<14> (Mcompar_main_reg.re_reg_cmp_gt0000_cy<14>)
  914. MUXCY:CI->O 1 0.026 0.000 Mcompar_main_reg.re_reg_cmp_gt0000_cy<15> (Mcompar_main_reg.re_reg_cmp_gt0000_cy<15>)
  915. MUXCY:CI->O 35 0.254 0.608 Mcompar_main_reg.re_reg_cmp_gt0000_cy<16> (Mcompar_main_reg.re_reg_cmp_gt0000_cy<16>)
  916. LUT6:I5->O 0 0.094 0.000 main_reg_re_reg_mux0001<0>1 (main_reg_re_reg_mux0001<0>)
  917. MUXCY:DI->O 1 0.362 0.000 Maddsub_main_reg.re_reg_mux0000_cy<0> (Maddsub_main_reg.re_reg_mux0000_cy<0>)
  918. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<1> (Maddsub_main_reg.re_reg_mux0000_cy<1>)
  919. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<2> (Maddsub_main_reg.re_reg_mux0000_cy<2>)
  920. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<3> (Maddsub_main_reg.re_reg_mux0000_cy<3>)
  921. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<4> (Maddsub_main_reg.re_reg_mux0000_cy<4>)
  922. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<5> (Maddsub_main_reg.re_reg_mux0000_cy<5>)
  923. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<6> (Maddsub_main_reg.re_reg_mux0000_cy<6>)
  924. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<7> (Maddsub_main_reg.re_reg_mux0000_cy<7>)
  925. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<8> (Maddsub_main_reg.re_reg_mux0000_cy<8>)
  926. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<9> (Maddsub_main_reg.re_reg_mux0000_cy<9>)
  927. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<10> (Maddsub_main_reg.re_reg_mux0000_cy<10>)
  928. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<11> (Maddsub_main_reg.re_reg_mux0000_cy<11>)
  929. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<12> (Maddsub_main_reg.re_reg_mux0000_cy<12>)
  930. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<13> (Maddsub_main_reg.re_reg_mux0000_cy<13>)
  931. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<14> (Maddsub_main_reg.re_reg_mux0000_cy<14>)
  932. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<15> (Maddsub_main_reg.re_reg_mux0000_cy<15>)
  933. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<16> (Maddsub_main_reg.re_reg_mux0000_cy<16>)
  934. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<17> (Maddsub_main_reg.re_reg_mux0000_cy<17>)
  935. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<18> (Maddsub_main_reg.re_reg_mux0000_cy<18>)
  936. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<19> (Maddsub_main_reg.re_reg_mux0000_cy<19>)
  937. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<20> (Maddsub_main_reg.re_reg_mux0000_cy<20>)
  938. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<21> (Maddsub_main_reg.re_reg_mux0000_cy<21>)
  939. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<22> (Maddsub_main_reg.re_reg_mux0000_cy<22>)
  940. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<23> (Maddsub_main_reg.re_reg_mux0000_cy<23>)
  941. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<24> (Maddsub_main_reg.re_reg_mux0000_cy<24>)
  942. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<25> (Maddsub_main_reg.re_reg_mux0000_cy<25>)
  943. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<26> (Maddsub_main_reg.re_reg_mux0000_cy<26>)
  944. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<27> (Maddsub_main_reg.re_reg_mux0000_cy<27>)
  945. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<28> (Maddsub_main_reg.re_reg_mux0000_cy<28>)
  946. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<29> (Maddsub_main_reg.re_reg_mux0000_cy<29>)
  947. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<30> (Maddsub_main_reg.re_reg_mux0000_cy<30>)
  948. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<31> (Maddsub_main_reg.re_reg_mux0000_cy<31>)
  949. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<32> (Maddsub_main_reg.re_reg_mux0000_cy<32>)
  950. MUXCY:CI->O 1 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<33> (Maddsub_main_reg.re_reg_mux0000_cy<33>)
  951. MUXCY:CI->O 0 0.026 0.000 Maddsub_main_reg.re_reg_mux0000_cy<34> (Maddsub_main_reg.re_reg_mux0000_cy<34>)
  952. XORCY:CI->O 1 0.357 0.000 Maddsub_main_reg.re_reg_mux0000_xor<35> (main_reg_re_reg_mux0000<35>)
  953. FD:D -0.018 main_reg.re_reg_35
  954. ----------------------------------------
  955. Total 17.930ns (11.686ns logic, 6.244ns route)
  956. (65.2% logic, 34.8% route)
  957.  
  958. =========================================================================
  959. Timing constraint: Default period analysis for Clock 'divisor<0>'
  960. Clock period: 4.536ns (frequency: 220.464MHz)
  961. Total number of paths / destination ports: 931 / 62
  962. -------------------------------------------------------------------------
  963. Delay: 4.536ns (Levels of Logic = 4)
  964. Source: shift_val_1 (LATCH)
  965. Destination: init_reg.re_reg_23 (LATCH)
  966. Source Clock: divisor<0> falling
  967. Destination Clock: divisor<0> falling
  968.  
  969. Data Path: shift_val_1 to init_reg.re_reg_23
  970. Gate Net
  971. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  972. ---------------------------------------- ------------
  973. LDCP:G->Q 100 0.736 1.209 shift_val_1 (shift_val_1)
  974. LUT6:I0->O 4 0.094 1.085 Sh10441 (Sh1044)
  975. LUT6:I0->O 1 0.094 0.000 init_reg_re_reg_mux0031<23>85_SW02 (init_reg_re_reg_mux0031<23>85_SW01)
  976. MUXF7:I0->O 1 0.251 0.973 init_reg_re_reg_mux0031<23>85_SW0_f7 (N1109)
  977. LUT6:I1->O 3 0.094 0.000 init_reg_re_reg_mux0031<23>85 (init_reg_re_reg_mux0031<23>)
  978. LDCP:D -0.071 init_reg.re_reg_23
  979. ----------------------------------------
  980. Total 4.536ns (1.269ns logic, 3.267ns route)
  981. (28.0% logic, 72.0% route)
  982.  
  983. =========================================================================
  984. Timing constraint: Default OFFSET IN BEFORE for Clock 'mclk1'
  985. Total number of paths / destination ports: 7 / 7
  986. -------------------------------------------------------------------------
  987. Offset: 2.334ns (Levels of Logic = 2)
  988. Source: go (PAD)
  989. Destination: i_0 (FF)
  990. Destination Clock: mclk1 rising
  991.  
  992. Data Path: go to i_0
  993. Gate Net
  994. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  995. ---------------------------------------- ------------
  996. IBUF:I->O 3 0.818 0.491 go_IBUF (go_IBUF)
  997. LUT4:I3->O 5 0.094 0.358 i_or00011 (i_or0001)
  998. FDS:S 0.573 i_0
  999. ----------------------------------------
  1000. Total 2.334ns (1.485ns logic, 0.849ns route)
  1001. (63.6% logic, 36.4% route)
  1002.  
  1003. =========================================================================
  1004. Timing constraint: Default OFFSET IN BEFORE for Clock 'divisor<0>'
  1005. Total number of paths / destination ports: 5382 / 99
  1006. -------------------------------------------------------------------------
  1007. Offset: 8.017ns (Levels of Logic = 10)
  1008. Source: divisor<26> (PAD)
  1009. Destination: init_reg.quo_reg_0 (LATCH)
  1010. Destination Clock: divisor<0> falling
  1011.  
  1012. Data Path: divisor<26> to init_reg.quo_reg_0
  1013. Gate Net
  1014. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  1015. ---------------------------------------- ------------
  1016. IBUF:I->O 69 0.818 0.923 divisor_26_IBUF (divisor_26_IBUF)
  1017. LUT4:I0->O 6 0.094 0.816 shift_val_or0000111 (N346)
  1018. LUT6:I2->O 8 0.094 0.518 init_reg_re_reg_mux0031<22>11 (N61)
  1019. LUT4:I3->O 4 0.094 1.085 init_reg_re_reg_mux0031<19>11 (N56)
  1020. LUT6:I0->O 179 0.094 0.731 init_reg_re_reg_mux0031<13>11 (N46)
  1021. LUT5:I3->O 51 0.094 0.920 init_reg_re_reg_or00011 (init_reg_re_reg_or0001)
  1022. LUT4:I0->O 3 0.094 0.721 init_reg_quo_reg_mux0031<0>41 (N332)
  1023. LUT6:I3->O 1 0.094 0.000 init_reg_quo_reg_mux0031<0>351 (init_reg_quo_reg_mux0031<0>351)
  1024. MUXF7:I1->O 1 0.254 0.480 init_reg_quo_reg_mux0031<0>35_f7 (init_reg_quo_reg_mux0031<0>35)
  1025. LUT6:I5->O 3 0.094 0.000 init_reg_quo_reg_mux0031<0>328 (init_reg_quo_reg_mux0031<0>)
  1026. LDCP:D -0.071 init_reg.quo_reg_0
  1027. ----------------------------------------
  1028. Total 8.017ns (1.824ns logic, 6.193ns route)
  1029. (22.8% logic, 77.2% route)
  1030.  
  1031. =========================================================================
  1032. Timing constraint: Default OFFSET OUT AFTER for Clock 'mclk1'
  1033. Total number of paths / destination ports: 1969726 / 64
  1034. -------------------------------------------------------------------------
  1035. Offset: 12.422ns (Levels of Logic = 54)
  1036. Source: i_re_0 (FF)
  1037. Destination: re<30> (PAD)
  1038. Source Clock: mclk1 rising
  1039.  
  1040. Data Path: i_re_0 to re<30>
  1041. Gate Net
  1042. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  1043. ---------------------------------------- ------------
  1044. FDS:C->Q 26 0.471 0.915 i_re_0 (i_re_0)
  1045. LUT4:I0->O 1 0.094 0.000 Mcompar_re_cmp_ge0010_lut<0> (Mcompar_re_cmp_ge0010_lut<0>)
  1046. MUXCY:S->O 1 0.372 0.000 Mcompar_re_cmp_ge0010_cy<0> (Mcompar_re_cmp_ge0010_cy<0>)
  1047. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<1> (Mcompar_re_cmp_ge0010_cy<1>)
  1048. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<2> (Mcompar_re_cmp_ge0010_cy<2>)
  1049. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<3> (Mcompar_re_cmp_ge0010_cy<3>)
  1050. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<4> (Mcompar_re_cmp_ge0010_cy<4>)
  1051. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<5> (Mcompar_re_cmp_ge0010_cy<5>)
  1052. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<6> (Mcompar_re_cmp_ge0010_cy<6>)
  1053. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<7> (Mcompar_re_cmp_ge0010_cy<7>)
  1054. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<8> (Mcompar_re_cmp_ge0010_cy<8>)
  1055. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<9> (Mcompar_re_cmp_ge0010_cy<9>)
  1056. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<10> (Mcompar_re_cmp_ge0010_cy<10>)
  1057. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<11> (Mcompar_re_cmp_ge0010_cy<11>)
  1058. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<12> (Mcompar_re_cmp_ge0010_cy<12>)
  1059. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<13> (Mcompar_re_cmp_ge0010_cy<13>)
  1060. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0010_cy<14> (Mcompar_re_cmp_ge0010_cy<14>)
  1061. MUXCY:CI->O 69 0.254 0.844 Mcompar_re_cmp_ge0010_cy<15> (re_cmp_ge0010)
  1062. LUT3:I0->O 57 0.094 1.201 re_mux0000<1>11111 (N519)
  1063. LUT6:I0->O 1 0.094 0.576 re_mux0000<1>81 (re_mux0000<1>81)
  1064. LUT6:I4->O 1 0.094 0.973 re_mux0000<1>150 (re_mux0000<1>150)
  1065. LUT6:I1->O 1 0.094 0.576 re_mux0000<1>209 (re_mux0000<1>)
  1066. LUT3:I1->O 1 0.094 0.000 Maddsub_re_share0000_lut<1> (Maddsub_re_share0000_lut<1>)
  1067. MUXCY:S->O 1 0.372 0.000 Maddsub_re_share0000_cy<1> (Maddsub_re_share0000_cy<1>)
  1068. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<2> (Maddsub_re_share0000_cy<2>)
  1069. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<3> (Maddsub_re_share0000_cy<3>)
  1070. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<4> (Maddsub_re_share0000_cy<4>)
  1071. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<5> (Maddsub_re_share0000_cy<5>)
  1072. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<6> (Maddsub_re_share0000_cy<6>)
  1073. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<7> (Maddsub_re_share0000_cy<7>)
  1074. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<8> (Maddsub_re_share0000_cy<8>)
  1075. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<9> (Maddsub_re_share0000_cy<9>)
  1076. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<10> (Maddsub_re_share0000_cy<10>)
  1077. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<11> (Maddsub_re_share0000_cy<11>)
  1078. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<12> (Maddsub_re_share0000_cy<12>)
  1079. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<13> (Maddsub_re_share0000_cy<13>)
  1080. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<14> (Maddsub_re_share0000_cy<14>)
  1081. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<15> (Maddsub_re_share0000_cy<15>)
  1082. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<16> (Maddsub_re_share0000_cy<16>)
  1083. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<17> (Maddsub_re_share0000_cy<17>)
  1084. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<18> (Maddsub_re_share0000_cy<18>)
  1085. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<19> (Maddsub_re_share0000_cy<19>)
  1086. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<20> (Maddsub_re_share0000_cy<20>)
  1087. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<21> (Maddsub_re_share0000_cy<21>)
  1088. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<22> (Maddsub_re_share0000_cy<22>)
  1089. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<23> (Maddsub_re_share0000_cy<23>)
  1090. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<24> (Maddsub_re_share0000_cy<24>)
  1091. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<25> (Maddsub_re_share0000_cy<25>)
  1092. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<26> (Maddsub_re_share0000_cy<26>)
  1093. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<27> (Maddsub_re_share0000_cy<27>)
  1094. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<28> (Maddsub_re_share0000_cy<28>)
  1095. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<29> (Maddsub_re_share0000_cy<29>)
  1096. XORCY:CI->O 1 0.357 0.973 Maddsub_re_share0000_xor<30> (re_share0000<30>)
  1097. LUT5:I0->O 1 0.094 0.336 re<30>1 (re_30_OBUF)
  1098. OBUF:I->O 2.452 re_30_OBUF (re<30>)
  1099. ----------------------------------------
  1100. Total 12.422ns (6.028ns logic, 6.394ns route)
  1101. (48.5% logic, 51.5% route)
  1102.  
  1103. =========================================================================
  1104. Timing constraint: Default path analysis
  1105. Total number of paths / destination ports: 368083575 / 64
  1106. -------------------------------------------------------------------------
  1107. Delay: 15.842ns (Levels of Logic = 74)
  1108. Source: divisor<1> (PAD)
  1109. Destination: re<30> (PAD)
  1110.  
  1111. Data Path: divisor<1> to re<30>
  1112. Gate Net
  1113. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  1114. ---------------------------------------- ------------
  1115. IBUF:I->O 230 0.818 0.740 divisor_1_IBUF (divisor_1_IBUF)
  1116. LUT2:I0->O 1 0.094 0.000 Mmult_re_mult0008_Madd_lut<1> (Mmult_re_mult0008_Madd_lut<1>)
  1117. MUXCY:S->O 1 0.372 0.000 Mmult_re_mult0008_Madd_cy<1> (Mmult_re_mult0008_Madd_cy<1>)
  1118. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<2> (Mmult_re_mult0008_Madd_cy<2>)
  1119. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<3> (Mmult_re_mult0008_Madd_cy<3>)
  1120. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<4> (Mmult_re_mult0008_Madd_cy<4>)
  1121. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<5> (Mmult_re_mult0008_Madd_cy<5>)
  1122. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<6> (Mmult_re_mult0008_Madd_cy<6>)
  1123. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<7> (Mmult_re_mult0008_Madd_cy<7>)
  1124. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<8> (Mmult_re_mult0008_Madd_cy<8>)
  1125. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<9> (Mmult_re_mult0008_Madd_cy<9>)
  1126. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<10> (Mmult_re_mult0008_Madd_cy<10>)
  1127. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<11> (Mmult_re_mult0008_Madd_cy<11>)
  1128. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<12> (Mmult_re_mult0008_Madd_cy<12>)
  1129. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<13> (Mmult_re_mult0008_Madd_cy<13>)
  1130. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<14> (Mmult_re_mult0008_Madd_cy<14>)
  1131. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<15> (Mmult_re_mult0008_Madd_cy<15>)
  1132. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<16> (Mmult_re_mult0008_Madd_cy<16>)
  1133. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<17> (Mmult_re_mult0008_Madd_cy<17>)
  1134. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<18> (Mmult_re_mult0008_Madd_cy<18>)
  1135. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<19> (Mmult_re_mult0008_Madd_cy<19>)
  1136. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<20> (Mmult_re_mult0008_Madd_cy<20>)
  1137. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<21> (Mmult_re_mult0008_Madd_cy<21>)
  1138. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<22> (Mmult_re_mult0008_Madd_cy<22>)
  1139. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<23> (Mmult_re_mult0008_Madd_cy<23>)
  1140. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<24> (Mmult_re_mult0008_Madd_cy<24>)
  1141. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<25> (Mmult_re_mult0008_Madd_cy<25>)
  1142. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<26> (Mmult_re_mult0008_Madd_cy<26>)
  1143. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<27> (Mmult_re_mult0008_Madd_cy<27>)
  1144. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<28> (Mmult_re_mult0008_Madd_cy<28>)
  1145. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0008_Madd_cy<29> (Mmult_re_mult0008_Madd_cy<29>)
  1146. XORCY:CI->O 1 0.357 0.336 Mmult_re_mult0008_Madd_xor<30> (re_mult0008<30>)
  1147. INV:I->O 1 0.238 0.000 Madd_re_not0001<30>1_INV_0 (Madd_re_not0001<30>)
  1148. MUXCY:S->O 0 0.372 0.000 Madd_re_sub0002_cy<30> (Madd_re_sub0002_cy<30>)
  1149. XORCY:CI->O 2 0.357 0.794 Madd_re_sub0002_xor<31> (re_sub0002<31>)
  1150. LUT4:I0->O 0 0.094 0.000 Mcompar_re_cmp_ge0010_lutdi15 (Mcompar_re_cmp_ge0010_lutdi15)
  1151. MUXCY:DI->O 69 0.590 0.844 Mcompar_re_cmp_ge0010_cy<15> (re_cmp_ge0010)
  1152. LUT3:I0->O 57 0.094 1.201 re_mux0000<1>11111 (N519)
  1153. LUT6:I0->O 1 0.094 0.576 re_mux0000<1>81 (re_mux0000<1>81)
  1154. LUT6:I4->O 1 0.094 0.973 re_mux0000<1>150 (re_mux0000<1>150)
  1155. LUT6:I1->O 1 0.094 0.576 re_mux0000<1>209 (re_mux0000<1>)
  1156. LUT3:I1->O 1 0.094 0.000 Maddsub_re_share0000_lut<1> (Maddsub_re_share0000_lut<1>)
  1157. MUXCY:S->O 1 0.372 0.000 Maddsub_re_share0000_cy<1> (Maddsub_re_share0000_cy<1>)
  1158. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<2> (Maddsub_re_share0000_cy<2>)
  1159. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<3> (Maddsub_re_share0000_cy<3>)
  1160. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<4> (Maddsub_re_share0000_cy<4>)
  1161. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<5> (Maddsub_re_share0000_cy<5>)
  1162. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<6> (Maddsub_re_share0000_cy<6>)
  1163. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<7> (Maddsub_re_share0000_cy<7>)
  1164. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<8> (Maddsub_re_share0000_cy<8>)
  1165. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<9> (Maddsub_re_share0000_cy<9>)
  1166. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<10> (Maddsub_re_share0000_cy<10>)
  1167. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<11> (Maddsub_re_share0000_cy<11>)
  1168. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<12> (Maddsub_re_share0000_cy<12>)
  1169. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<13> (Maddsub_re_share0000_cy<13>)
  1170. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<14> (Maddsub_re_share0000_cy<14>)
  1171. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<15> (Maddsub_re_share0000_cy<15>)
  1172. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<16> (Maddsub_re_share0000_cy<16>)
  1173. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<17> (Maddsub_re_share0000_cy<17>)
  1174. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<18> (Maddsub_re_share0000_cy<18>)
  1175. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<19> (Maddsub_re_share0000_cy<19>)
  1176. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<20> (Maddsub_re_share0000_cy<20>)
  1177. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<21> (Maddsub_re_share0000_cy<21>)
  1178. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<22> (Maddsub_re_share0000_cy<22>)
  1179. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<23> (Maddsub_re_share0000_cy<23>)
  1180. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<24> (Maddsub_re_share0000_cy<24>)
  1181. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<25> (Maddsub_re_share0000_cy<25>)
  1182. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<26> (Maddsub_re_share0000_cy<26>)
  1183. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<27> (Maddsub_re_share0000_cy<27>)
  1184. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<28> (Maddsub_re_share0000_cy<28>)
  1185. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<29> (Maddsub_re_share0000_cy<29>)
  1186. XORCY:CI->O 1 0.357 0.973 Maddsub_re_share0000_xor<30> (re_share0000<30>)
  1187. LUT5:I0->O 1 0.094 0.336 re<30>1 (re_30_OBUF)
  1188. OBUF:I->O 2.452 re_30_OBUF (re<30>)
  1189. ----------------------------------------
  1190. Total 15.842ns (8.493ns logic, 7.349ns route)
  1191. (53.6% logic, 46.4% route)
  1192.  
  1193. =========================================================================
  1194.  
  1195.  
  1196. Total REAL time to Xst completion: 1421.00 secs
  1197. Total CPU time to Xst completion: 1420.88 secs
  1198.  
  1199. -->
  1200.  
  1201.  
  1202. Total memory usage is 653248 kilobytes
  1203.  
  1204. Number of errors : 0 ( 0 filtered)
  1205. Number of warnings : 100 ( 0 filtered)
  1206. Number of infos : 2 ( 0 filtered)
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