gol_dec_tb

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-- Company:
-- Engineer:
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-- Create Date: 23.02.2024 22:08:25
-- Design Name:
-- Module Name: gol_dec_tb - rtl
-- Project Name:
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-- Tool Versions:
-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity gol_dec_tb is
--  Port ( );
end gol_dec_tb;

architecture rtl of gol_dec_tb is
    -- Declare the component under test
    component gol_dec is
        port (
            codeword_i : in  std_logic_vector(5 downto  0);
            symbol_o   : out std_logic_vector(3 downto  0)
        );
    end component gol_dec;

    -- Declare signals for the testbench
    signal tb_codeword_i : std_logic_vector(5 downto  0);
    signal tb_symbol_o   : std_logic_vector(3 downto  0);

begin
    -- Instantiate the component under test
    dut: gol_dec
        port map (
            codeword_i => tb_codeword_i,
            symbol_o   => tb_symbol_o
        );

    -- Testbench stimulus process
    stim_proc: process
    begin
        -- Initialize inputs
        tb_codeword_i <= "100000";
        wait for  10 ns;

        tb_codeword_i <= "001000";
        wait for  10 ns;

        tb_codeword_i <= "000110";
        wait for  10 ns;

        tb_codeword_i <= "001100";
        wait for  10 ns;

        tb_codeword_i <= "111000";
        wait for  10 ns;

        tb_codeword_i <= "010100";
        wait for  10 ns;
        -- End the simulation
        wait;
    end process stim_proc;
end rtl;