Edgedetect2 but within the same clock cycle

module top_module (
    input clk,
    input [7:0] in,
    output reg [7:0] anyedge
);
    reg [7:0] aux;

    always @(posedge clk) begin
        anyedge <= aux ^ in;  // Detect edge by XORing current and previous state
        aux <= in;            // Update aux with the current state of 'in'
    end
endmodule