count_free

`timescale 1ns/1ps

module count_free (
    input clk,
    input rst,
    input start_req_i,
    input start_data_i,
    input ready_i,
    output reg result_rsp_o,
    output reg busy_o
);

parameter IDLE =0, RECEIVE_DATA = 1, CHECK_DATA = 2, DONE = 3;
reg[5:0] amount_of_edinichkas = 0;
reg[5:0] check_amount_of_edinichkas = 0;
reg[31:0] count_of_ticks = 0;
reg[31:0] data = 0;
reg[31:0] temp_data = 0;
reg[1:0] state;
reg[1:0] next_state = IDLE;

always @(negedge clk) begin
    case (state)
        IDLE: begin
            next_state = RECEIVE_DATA;
            busy_o = 0;
            result_rsp_o = 0;
        end
        RECEIVE_DATA : begin
            next_state = CHECK_DATA;
            busy_o = 1;
        end
        CHECK_DATA : begin
            next_state = DONE;
            busy_o = 1;
        end
        DONE : begin
            next_state = IDLE;
            result_rsp_o = 1;
            busy_o = 0;
        end
endcase
end

always @(posedge clk or posedge rst) begin
    if (rst) begin
        state <= IDLE;
        amount_of_edinichkas <= 0;
        check_amount_of_edinichkas <= 0;
        data <= 0;
        count_of_ticks <= 0;
        temp_data <= 0;

    end
end

always @(posedge clk) begin
    case (state)
        IDLE : begin
            if (start_req_i) begin
                data <= start_data_i;
                state <= next_state;
            end
        end
        RECEIVE_DATA : begin
            if (start_data_i) begin
                amount_of_edinichkas <= amount_of_edinichkas + 1;
            end
            if (start_req_i) begin
                data <= (data << 1) + start_data_i;
            end else begin
                temp_data <= data;
                state <= next_state;
            end
        end
        CHECK_DATA: begin
            if (count_of_ticks == data && amount_of_edinichkas == check_amount_of_edinichkas) begin
                state <= next_state;
            end
            else begin
                count_of_ticks <= count_of_ticks + 1;
                if (temp_data[0] & temp_data !=0) begin
                    check_amount_of_edinichkas <= check_amount_of_edinichkas + 1;
                end
                temp_data <= temp_data >> 1;
            end
        end
        DONE : begin
            count_of_ticks <= 0;
            if (ready_i) begin
                state <= next_state;
            end
        end
        endcase
end
endmodule