ex4_37

//必考!(第一題) 給圖，跑出一樣的Waveform
module Add_Sub_4bit(output [3:0] s,output c4,input[3:0]a,b,input M);
    wire[3:0] b_bar;
    xor G0(b_bar[0],b[0],M);
    xor G1(b_bar[1],b[1],M);
    xor G2(b_bar[2],b[2],M);
    xor G3(b_bar[3],b[3],M);
    wire c1,c2,c3;

    //Ripple Adder

     FullAdder M0(s[0],c1,a[0],b_bar[0],M);
    FullAdder M1(s[1],c2,a[1],b_bar[1],c1);
    FullAdder M2(s[2],c3,a[2],b_bar[2],c2);
    FullAdder M3(s[3],c4,a[3],b_bar[3],c3);

    //前瞻
    //cla_4bit M0(s,c4,a,b_bar,M);

endmodule

//前瞻
module cla_4bit(output[3:0]s,output c4,input[3:0]a,b,input c0);
    wire[3:0] p,g;
    HalfAdder M0 (p[0],g[0],a[0],b[0]);
    HalfAdder M1 (p[1],g[1],a[1],b[1]);
    HalfAdder M2 (p[2],g[2],a[2],b[2]);
    HalfAdder M3 (p[3],g[3],a[3],b[3]);

    assign c1=g[0]|(p[0]&c0);
    assign c2=g[1]|(p[1]&g[0])|(p[1]&p[0]&c0);
    assign c3=g[2]|(p[2]&g[1])|(p[2]&p[1]&g[0])|(p[2]&p[1]&p[0]&c0);
    assign c4=g[3]|(p[3]&g[2])|(p[3]&p[2]&g[1])|(p[3]&p[2]&p[1]&g[0]) | (p[3]&p[2]&g[1]&g[0]&c0);

    assign s[3]=c3^p[3];
    assign s[2]=c2^p[2];
    assign s[1]=c1^p[1];
    assign s[0]=c0^p[0];

endmodule


module HalfAdder(output s,c,input a,b);
    xor G0(s,a,b);
    and G1(c,a,b);
endmodule

module FullAdder(output s,co,input a,b,ci);
    wire s1,c1,c2;
    HalfAdder M0(s1,c1,a,b);
    HalfAdder M1(s,c2,s1,ci);
    or G0(co,c1,c2);
endmodule


module t_Add_Sub_4bit();
    wire[3:0] s;
    wire c;
    reg[3:0] a;
    reg[3:0] b;
    reg M;

    Add_Sub_4bit M0(s,c,a,b,M);
    initial begin
            #20
            a=4'b1011;
            b=4'b0101;
            M=0;
            #20
            a=4'b0100;
            #20
            M=1;
            #20
            a=4'b0011;
            #20 $finish;
    end
endmodule