Syntax

task taskname;
   input s;
   input logic [2:0] t;
   output u;

    begin
        // Task statements
    end
endtask

function [2:0] functionname;
    input s;
    integer t;
    parameter u;
    reg [2:0] v;

    begin
        // Function statements
        // Functions outputs assignments
    end
endfunction

task outputs;
    input [2:0] s;
    integer h = 0:
    output t;

    begin
        repeat (3) begin
            t = h;     // Uses blocking to only works when every after delay only
            t = t + 1;
            #10;

            t <= s > 2'b10; // Uses non-blocking to simultaneously outputs this with the above output without waiting for the delay
        end
    end
endtask

function [2:0] outputs;
    input [2:0] s;

    begin
        if (s[3] == 1'b1) begin // If statement to convert any even data and only outputs odd ones
            outputs = ~s + 1'b1;
        end
        else begin
            outputs = s;
        end
    end
endfunction

always @(posedge clk) begin
    outputs(3'b111);
end

logic [2:0] result;
always @(posedge clk) begin
    result = outputs(data[2:0]);
end