probe-rs v0.25 JLink GD32E5

$ cargo-1.80 run -- info --protocol jtag
    Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.32s
     Running `target/debug/probe-rs info --protocol jtag`
Probing target via JTAG

ARM Chip with debug port Default:
Debug Port: DPv1, MINDP, DP Designer: ARM Ltd
└── 0 MemoryAP (AmbaAhb5)
    └── ROM Table (Class 1), Designer: GigaDevice Semiconductor (Beijing)
        ├── ROM Table (Class 1), Designer: ARM Ltd
        │   ├── Cortex-M33 SCS  (Coresight Component)
        │   │   └── CPUID
        │   │       ├── IMPLEMENTER: ARM Ltd
        │   │       ├── VARIANT: 0
        │   │       ├── PARTNO: Cortex-M33
        │   │       └── REVISION: 4
        │   ├── Cortex-M33 DWT  (Coresight Component)
        │   ├── Cortex-M33 BPU  (Coresight Component)
        │   └── Cortex-M33 ITM  (Coresight Component)
        └── Cortex-M33 TPIU (Coresight Component)


RISC-V Chip:
  IDCODE: 0000000000
    Version:      0
    Part:         0
    Manufacturer: 0 (Unknown Manufacturer Code)
Error showing Xtensa chip information: An error originating from the DebugProbe occurred.

Caused by:
    Invalid instruction register access: 30

$ cargo-1.80 run -- info --protocol swd
    Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.32s
     Running `target/debug/probe-rs info --protocol swd`
Probing target via SWD

ARM Chip with debug port Default:
Debug Port: DPv2, MINDP, Designer: GigaDevice Semiconductor (Beijing), Part: 0x3233, Revision: 0x0, Instance: 0x00
└── 0 MemoryAP (AmbaAhb5)
    └── ROM Table (Class 1), Designer: GigaDevice Semiconductor (Beijing)
        ├── ROM Table (Class 1), Designer: ARM Ltd
        │   ├── Cortex-M33 SCS  (Coresight Component)
        │   │   └── CPUID
        │   │       ├── IMPLEMENTER: ARM Ltd
        │   │       ├── VARIANT: 0
        │   │       ├── PARTNO: Cortex-M33
        │   │       └── REVISION: 4
        │   ├── Cortex-M33 DWT  (Coresight Component)
        │   ├── Cortex-M33 BPU  (Coresight Component)
        │   └── Cortex-M33 ITM  (Coresight Component)
        └── Cortex-M33 TPIU (Coresight Component)


Debugging RISC-V targets over SWD is not supported. For these targets, JTAG is the only supported protocol. RISC-V specific information cannot be printed.
Debugging Xtensa targets over SWD is not supported. For these targets, JTAG is the only supported protocol. Xtensa specific information cannot be printed.