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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
- library work;
- use work.proc_config.all;
- entity mipsCpu is
- generic(PROG_FILE_NAME : string;
- DATA_FILE_NAME : string
- );
- port(clk : in std_logic;
- rst : in std_logic;
- -- instruction insertion ports
- testMode_debug : in std_logic;
- testInstruction_debug : in std_logic_vector(31 downto 0);
- -- ram access ports
- ramInsertMode_debug : in std_logic; -- wenn das Signal = 1 , werden alle drei unteren weitergegeben; wenn 0 - drei MUX (um zu entscheiden ob unsere oder debug Signale genutyt werden sollen)
- ramWriteEn_debug : in std_logic;
- ramWriteAddr_debug : in std_logic_vector(LOG2_NUM_RAM_ELEMENTS - 1 downto 0);
- ramWriteData_debug : in std_logic_vector(RAM_ELEMENT_WIDTH - 1 downto 0);
- ramElements_debug : out ram_elements_type;
- -- register file access port
- registers_debug : out reg_vector_type;
- -- intermediate result ports
- pc_next_debug : out std_logic_vector(PC_WIDTH - 1 downto 0);
- pc7SegDigits_debug : out pc_7seg_digits_type
- );
- end mipsCpu;
- architecture structural of mipsCpu is
- --Signale Instruction Mux
- signal instruction_rom : std_logic_vector(31 downto 0);
- signal instruction : std_logic_vector(31 downto 0);
- --Signale Instruction Memory
- signal addr_pc : std_logic_vector(31 downto 0);
- --Signale Control
- signal regDst : std_logic;
- signal branch : std_logic;
- signal memRead : std_logic;
- signal memToReg : std_logic;
- signal aluOp : std_logic_vector(1 downto 0);
- signal memWrite : std_logic;
- signal aluSrc : std_logic;
- signal regWrite : std_logic; --in bei RegisterFile
- --Signale Registers (mittig)
- signal writeReg : std_logic_vector(4 downto 0);
- signal writeData : std_logic_vector(31 downto 0);
- signal readData1 : std_logic_vector(31 downto 0);
- signal readData2 : std_logic_vector(31 downto 0);
- --Signale RAM
- signal ramWriteEn : std_logic;
- signal ramWriteAddr : std_logic_vector(31 downto 0);
- signal ramWriteData : std_logic_vector(31 downto 0);
- --Signale Sign Extend
- signal signExtendNumber : std_logic_vector(31 downto 0);
- --Signale Shift Left 2
- signal shiftedNumber : std_logic_vector(31 downto 0);
- --Signale ALU Control
- signal operation : std_logic_vector(3 downto 0);
- --Signale ALU
- signal aluResult : std_logic_vector(4 downto 0);
- --zusaetzliche Signale
- signal muxalu : std_logic_vector(3 downto 0); -- auch der 4. MUX
- signal mux3 : std_logic_vector();
- signal muxRamOut : std_logic_vector(); -- auch der 2. Mux
- signal muxRamIn : std_logic_vector();
- signal or_out : std_logic;
- --Signale Addierer
- signal add2 : std_logic_vector(31 downto 0);
- signal add1: std_logic_vector(31 downto 0);
- begin
- with testMode_debug select
- instruction <= testInstruction_debug when "1" else instruction_rom;
- -- Beschreibung der MIPS-CPU ergänzen
- CONTROL: entity work.mipsCtrl(structural) --Beschreibung des Control MIPS
- port map( op(5 downto 0) => testInstruction_debug(31 downto 26),
- regDst => regDst,
- branch => branch,
- memRead => memRead,
- aluOp(1 downto 0) => aluOp(1 downto 0),
- memWrite => memWrite,
- aluSrc => aluSrc,
- regWrite => regWrite);
- or_out <= branch or zero;
- --ramInsertMode_debug : in std_logic; -- wenn das Signal = 1 , werden alle drei unteren weitergegeben; wenn 0 - drei MUX (um zuentscheiden ob unsere oder debug Signale genutyt werden sollen)
- --ramWriteEn_debug : in std_logic;
- --ramWriteAddr_debug : in std_logic_vector(LOG2_NUM_RAM_ELEMENTS - 1 downto 0);
- --ramWriteData_debug : in std_logic_vector(RAM_ELEMENT_WIDTH - 1 downto 0);
- with ramInsertMode_debug select -- Beschreibung des MUX vor dem RAM (Kommentar oben)
- ramWriteEn <= ramWriteEn_debug when '1',
- memWrite when '0';
- with ramInsertMode_debug select
- ramWriteAddr <= ramWriteAddr_debug when '1',
- aluResult when '0';
- with ramInsertMode_debug select
- ramWriteData <= ramWriteData_debug when '1',
- reafFata2 when '0';
- with regDst select --Beschreibung des ersten MUXs
- writeReg <= testInstruction_debug(20 downto 16) when '0',
- testInstruction_debug(15 downto 11) when '1';
- with memToReg select -- Beschreibung zweites MUXs
- muxRamOut <= ramElements_debug when '0',
- aluRes when '1';
- with or_out select -- Beschreibung des dritten MUXs
- mux3 <= add1 when '0',
- add2 when '1';
- with aluSrc select -- Beschreibung des vierten MUXs
- muxalu <= resdData2 when '0',
- signExtendNumber when '1';
- signextend : entity work.signExtend.vhd --Beschreibung des SignExtend
- generic map(INPUT_WIDTH => '16',
- OUTPUT_WIDTH => '32')
- port map(number => testInstruction_debug(15 downto 0),
- signExtNumber(31 downto 0) => signExtendNumber(31 downto 0));
- shiftleft2 : entity work.leftShifter --Beschreibung ShiftLeft
- generic map(WIDTH => '32'
- SHIFT_AMOUNT => '2')
- port map(number(31 downto 0) => signExtendNumber(WIDTH - 1 downto 0)
- shiftedNumber(31 downto 0) => shiftedNumber(31 downto 0));
- alucontrol : entity work.aluCtrl --Beschreibung ALU Control
- port map(f(5 downto 0) => testInstruction_debug(5 downto 0),
- aluOp(1 downto 0) => aluOp(1 downto 0),
- operation(3 downto 0) => peration(3 downto 0));
- alu : entity work.mipsAlu -- Beschreibung ALU
- port map(ctrl(3 downto 0) => operation(3 downto 0),
- a(4 downto 0) => readData1(4 downto 0),
- b(4 downto 0) => muxalu(4 downto 0),
- result(4 downto 0) => aluResult(4 downto 0),
- zero => zero);
- -- Beschreibung Addierers
- add1 <= 4 + addr_pc;
- add2 <= add1 + shiftedNumber;
- --Beschreibung BinToChars
- binToChar1 : entity work.bin2Char
- port(bin => addr_pc(3 downto 0);
- bitmask => pc7SegDigits_debug(0);
- binToChar2 : entity work.bin2Char
- port(bin => addr_pc(7 downto 4);
- bitmask => pc7SegDigits_debug(1);
- binToChar3 : entity work.bin2Char
- port(bin => addr_pc(11 downto 8);
- bitmask => pc7SegDigits_debug(2);
- binToChar4 : entity work.bin2Char
- port(bin => addr_pc(15 downto 12);
- bitmask => pc7SegDigits_debug(3);
- --Beschreibung von RegFile
- regFile : entity.work.regFile
- generic map(NUM_REGS => '32';
- LOG2_NUM_REGS => '5';
- REG_WIDTH => '32');
- port map(clk => clk,
- rst => rst,
- readAddr1 => instructions(25 downto 21),-- in
- readData1 => readData1, --out
- readAddr2 => instructions(20 downto 16), --in
- readData2 => readData2, --out
- writeEn => regWrite; -- Eingang hier, Ausgang von MIPS Control
- writeAddr => writeReg, -- eingang WriteRegister, Ausgang des ersten MUXs
- writeData => muxRamOut, -- eingang WriteData = Ausgang des zweiten MUXs
- reg_vect_debug => registers_debug;)
- -- Instruction Memory
- INSTR_ROM: entity work.flashROM(behavioral) -- nutzen Worte (4 Bits) -- PC auf 4 teilen
- generic map(NUM_ELEMENTS => ,
- LOG2_NUM_ELEMENTS => ,
- ELEMENT_WIDTH => '32',
- INIT_FILE_NAME => PROG_FILE_NAME)
- port map(address => addr_pc -- pc_next_debug?,
- readData => instruction_rom);
- -- Data Memory
- DATA_RAM: entity work.flashRAM(behavioral)
- generic map(NUM_ELEMENTS => '1024' ,
- LOG2_NUM_ELEMENTS => '10' ,
- ELEMENT_WIDTH => '32',
- INIT_FILE_NAME => DATA_FILE_NAME)
- port map(clk => invClk,
- address => ramWriteAddr,
- writeEn => ramWriteEn, -
- writeData => ramWriteData,
- readEn => memRead,
- readData => muxRamOut,
- ramElements_debug => ramElements_debug);
- end architecture;
- --Kommentare und Fragen:
- --1. Muss man PC aus einer entity instanzieirung oder selber schreiben? pc_next_debug = Ausgang, Augang des dritten MUXes = Eingang
- --
- --3. Fehlt: Verstaendnis zum PC, INSTR_ROM Generic
- --4 Ueberall Laenge checken und mit Vorgaben vergleichen
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