LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
Entity Tester is
Port (
    r_CPU_cs        :OUT    std_logic;
    r_CPU_RAM_data_in   :OUT    std_logic_vector (0 to 63);
    r_CPU_RAM_address   :OUT    std_logic_vector (0 to 15);
    r_output        :IN std_logic_vector (0 to 2);
    r_ready         :OUT    std_logic; -- 0 ничё не меняется
    r_request       :OUT    std_logic;
    clk         :OUT    std_logic;
    r_address_DMA_in        :OUT    std_logic_vector (0 to 15);
    r_reset         :OUT    std_logic);

END Tester;

Architecture Test of Tester IS
CONSTANT second     : TIME := 10 ns;
CONSTANT second_100     : TIME := 1000 ns;
CONSTANT second_3   : TIME := 30 ns;
CONSTANT second_2   : TIME := 20 ns;
CONSTANT second_10  : TIME := 100 ns;
Begin

synchronizer : PROCESS --тактовая
BEGIN
    clk <= '0';
    WAIT FOR second;
    clk <= '1';
    WAIT FOR second;
END PROCESS;

work:
Process
Begin
wait for second;
r_ready <= '0';
r_request <= '0';
r_reset<= '1';
wait for second_2;
r_reset <= '0';
wait for second_2;
r_CPU_cs <= '0';
wait for second_2;
r_CPU_RAM_address <= x"0064";
r_CPU_RAM_data_in <= x"000F01A7006800FA";
wait for second_2;
r_CPU_RAM_address <= x"00FA";
r_CPU_RAM_data_in <= x"012C01F400400000";
wait for second_2;
r_CPU_cs <= '1';
r_CPU_RAM_address <= x"0000";
r_CPU_RAM_data_in <= x"0000000000000000";
wait for second_2;
r_request <= '1';
r_address_DMA_in    <= x"0064";
wait for second_2;
r_request <= '0';
r_address_DMA_in <= x"0000";
wait for second_10;
r_ready <= '1';
wait for second_10;
r_ready<= '0';
wait for second_100;
end process;

end Test;