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stiansjogren

Untitled

Jun 18th, 2016
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  1. 1 Questions
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  5. 1.1
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  8. process(clk_en,di,dsi,rstn)
  9. begin
  10. if rstn='0' then
  11. do<=(others=>'0');
  12. elsif clk_en= '1'then
  13. if dsi='1'then
  14. do<=di;
  15. end if;
  16. end if;
  17. end process;
  18.  
  19. - This process is a syncroeous process because the output does not only depent on the input, but also of the past values of inputs.
  20. - Although the process does not contain any syntactical errors, the functionality is not useful. I think the process tries to implement a
  21. DFF with asyncroneus reset. Non-syntactical errors: clk signal not in sensitivity list and the DFF does not operate on rising edge of the clock.
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  24. Improved version:
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  26.  
  27. process(clk ,clk_en,di,dsi,rstn)
  28. begin
  29. if rising_edge(clk) then
  30. if rstn='0' then
  31. do<=(others=>'0');
  32. elsif clk_en= '1'then
  33. if dsi='1'then
  34. do<=di;
  35. end if;
  36. end if;
  37. end if;
  38. end process;
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