VHDL Gray Code to Binary

library IEEE;
use IEEE.STD_LOGIC;
use IEEE.NUMERIC_STD.ALL;

-- Entity to convert Gray code to binary
entity gray_code_converter is
    Generic (
        WIDTH : positive := 4
    );
    Port (
        clk : in  STD_LOGIC;
        rst : in  STD_LOGIC;
        gray : in  STD_LOGIC_VECTOR (WIDTH-1 downto 0);
        binary : out  STD_LOGIC_VECTOR (WIDTH-1 downto 0)
    );
end gray_code_converter;

architecture Behavioral of gray_code_converter is
    signal binary_int : STD_LOGIC_VECTOR (WIDTH-1 downto 0);
begin
    -- Convert Gray code to binary
    process(clk)
    begin
        if rising_edge(clk) then
            if rst = '1' then
                binary_int <= (others => '0');
            else
                -- MSB of binary output is the same as MSB of Gray code
                binary_int(binary_int'high) <= gray(gray'high);

                -- Calculate remaining bits of binary output
                for i in binary_int'high-1 downto 0 loop
                    binary_int(i) <= gray(i+1) xor gray(i);
                end loop;
            end if;
        end if;
    end process;

    -- Pipeline the output
    process(clk)
    begin
        if rising_edge(clk) then
            if rst = '1' then
                binary <= (others => '0');
            else
                binary <= binary_int;
            end if;
        end if;
    end process;
end Behavioral;