tb_memoria_de_retenção

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-- Company:
-- Engineer:
--
-- Create Date: 05/17/2019 10:12:44 PM
-- Design Name:
-- Module Name: tb_mem_ret - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity tb_mem_ret is
--  Port ( );
end tb_mem_ret;

architecture Behavioral of tb_mem_ret is

    component mem_ret is
    Port ( clk  : in STD_LOGIC;
           rst   : in STD_LOGIC;
           sw   : in STD_LOGIC_VECTOR (3 downto 0);
           lib  : in STD_LOGIC;
           sol  : out STD_LOGIC;
           ad   : out STD_LOGIC_VECTOR (1 downto 0));
   end component;

      signal sw   : STD_LOGIC_VECTOR (3 downto 0):= (others => '0');
      signal clk  : STD_LOGIC := '0';
      signal rst  : STD_LOGIC := '0';
      signal lib  : STD_LOGIC := '0';
      signal sol  : STD_LOGIC := '0';
      signal ad   : STD_LOGIC_VECTOR (1 downto 0) := "00";
      constant clk_period : time := 10ns;

begin
tb_pm: mem_ret port map( clk  => clk,
                         rst  => rst,
                         sw   => sw,
                         lib  => lib,
                         sol  => sol,
                         ad   => ad );

    clk_stimulus: process
    begin
        wait for clk_period/2;
            clk <= '0';
        wait for clk_period/2;
            clk <= '1';
    end process;

stimulus: process
    begin
        wait for 5*clk_period;
                sw <= "1111";
            wait for 2*clk_period;
                sw <= "0000";
            wait for 5* clk_period;
                lib <= '1';
            wait for 2*clk_period;
                lib <= '0';
            wait for 8* clk_period;
                lib <= '1';
            wait for 2*clk_period;
                lib <= '0';
            wait for 2*clk_period;
                lib <= '1';
            wait for 2*clk_period;
                lib <= '0';
            wait for 2*clk_period;
                lib <= '1';
            wait for 2*clk_period;
                lib <= '0';
                sw <= "1001";
    end process;


end Behavioral;