dekoder38

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- warning: this file will not be saved if:
--     * following entity block contains any syntactic errors (e.g. port list isn't separated with ; character)
--     * following entity name and current file name differ (e.g. if file is named mux41 then entity must also be named mux41 and vice versa)
ENTITY dekoder38 IS PORT(
    e: IN std_logic;
    a0, a1, a2: IN std_logic;
    y: OUT std_logic_vector(0 to 7)
);
END dekoder38;

ARCHITECTURE arch OF dekoder38 IS
    signal c1,c2,c3,c4: std_logic;
    signal o1,o2,o3,o4,o5,o6,o7,o8: std_logic;
BEGIN
    d1: entity work.dekoder24 port map (e,a2,a1,c1,c2,c3,c4);

    d2: entity work.dekoder12 port map (c1,a0,o1,o2);
    d3: entity work.dekoder12 port map (c2,a0,o3,o4);
    d4: entity work.dekoder12 port map (c3,a0,o5,o6);
    d5: entity work.dekoder12 port map (c4,a0,o7,o8);

    y <= o1 & o2 & o3 & o4 & o5 & o6 & o7 & o8;

END arch;