Branch_ALU

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity branch_alu is
    port (
        current_instruction     : in  std_logic_vector(63 downto 0); -- Note: current instruction needs to be divided by 4 technically.
        next_instruction_offset  : in std_logic_vector(63 downto 0);
        next_instruction  : out std_logic_vector(63 downto 0)
    );
end entity branch_alu;

architecture dataflow of branch_alu is
    signal next_instruction_offset_shifted : std_logic_vector(63 downto 0);
begin
    -- Shift next_instruction_offset to multiply it by 4
    next_instruction_offset_shifted <= std_logic_vector(shift_left(signed(next_instruction_offset), 2));

    -- Add result together
    next_instruction <= std_logic_vector(signed(next_instruction_offset_shifted) + signed(current_instruction));
end architecture dataflow;