SR FLIP-FLOP SYNC

-- design.vhd

library IEEE;
use IEEE.std_logic_1164.all;

entity sr_sync is
    port(S, R, clock : in std_logic;
         Q, Qn : out std_logic);
end entity;

architecture sr_sync_arch of sr_sync is
begin
    process(clock)
    begin
        if(clock'event and clock = '1') then
            if(S = '0' and R = '0') then
                Q <= Q;
                Qn <= Qn;
            elsif(S = '0' and R = '1') then
                Q <= '0';
                Qn <= '1';
            elsif(S = '1' and R = '0') then
                Q <= '1';
                Qn <= '0';
            elsif(S = '1' and R = '1') then
                Q <= '0';
                Qn <= '0';
            end if;
        end if;
    end process;
end architecture sr_sync_arch;


-- testbench.vhd

library IEEE;
use IEEE.std_logic_1164.all;

entity sr_sync_tb is
end entity;

architecture sr_sync_tb_arch of sr_sync_tb is
    signal S, R, clock, Q, Qn : std_logic;
begin
    DUT1 : entity work.sr_sync(sr_sync_arch)
           port map(S, R, clock, Q, Qn);

    CLOCK_PROCESS : process
    begin
        clock <= '0'; wait for 10ns;
        clock <= '1'; wait for 10ns;
    end process CLOCK_PROCESS;

    STIMULUS : process
    begin
        S <= 'X'; R <= 'X'; wait for 10ns;
        S <= 'X'; R <= 'X'; wait for 10ns;
        S <= '0'; R <= '0'; wait for 10ns;
        S <= '0'; R <= '0'; wait for 10ns;
        S <= '0'; R <= '1'; wait for 10ns;
        S <= '0'; R <= '1'; wait for 10ns;
        S <= '1'; R <= '0'; wait for 10ns;
        S <= '1'; R <= '0'; wait for 10ns;
        S <= '1'; R <= '1'; wait for 10ns;
        S <= '1'; R <= '1'; wait for 10ns;
    end process;
end architecture sr_sync_tb_arch;