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vedic_div32.syr.0565e71464c62be02969537ea76348032df8688e

MasWag
May 11th, 2015
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  1. Release 14.4 - xst P.49d (lin64)
  2. Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
  3. -->
  4. Parameter TMPDIR set to xst/projnav.tmp
  5.  
  6.  
  7. Total REAL time to Xst completion: 4.00 secs
  8. Total CPU time to Xst completion: 0.09 secs
  9.  
  10. -->
  11. Parameter xsthdpdir set to xst
  12.  
  13.  
  14. Total REAL time to Xst completion: 4.00 secs
  15. Total CPU time to Xst completion: 0.09 secs
  16.  
  17. -->
  18. Reading design: vedic_div32.prj
  19.  
  20. TABLE OF CONTENTS
  21. 1) Synthesis Options Summary
  22. 2) HDL Compilation
  23. 3) Design Hierarchy Analysis
  24. 4) HDL Analysis
  25. 5) HDL Synthesis
  26. 5.1) HDL Synthesis Report
  27. 6) Advanced HDL Synthesis
  28. 6.1) Advanced HDL Synthesis Report
  29. 7) Low Level Synthesis
  30. 8) Partition Report
  31. 9) Final Report
  32. 9.1) Device utilization summary
  33. 9.2) Partition Resource Summary
  34. 9.3) TIMING REPORT
  35.  
  36.  
  37. =========================================================================
  38. * Synthesis Options Summary *
  39. =========================================================================
  40. ---- Source Parameters
  41. Input File Name : "vedic_div32.prj"
  42. Input Format : mixed
  43. Ignore Synthesis Constraint File : NO
  44.  
  45. ---- Target Parameters
  46. Output File Name : "vedic_div32"
  47. Output Format : NGC
  48. Target Device : xc5vlx50t-1-ff1136
  49.  
  50. ---- Source Options
  51. Top Module Name : vedic_div32
  52. Automatic FSM Extraction : YES
  53. FSM Encoding Algorithm : Auto
  54. Safe Implementation : No
  55. FSM Style : LUT
  56. RAM Extraction : Yes
  57. RAM Style : Auto
  58. ROM Extraction : Yes
  59. Mux Style : Auto
  60. Decoder Extraction : YES
  61. Priority Encoder Extraction : Yes
  62. Shift Register Extraction : YES
  63. Logical Shifter Extraction : YES
  64. XOR Collapsing : YES
  65. ROM Style : Auto
  66. Mux Extraction : Yes
  67. Resource Sharing : NO
  68. Asynchronous To Synchronous : NO
  69. Use DSP Block : Auto
  70. Automatic Register Balancing : No
  71.  
  72. ---- Target Options
  73. LUT Combining : Auto
  74. Reduce Control Sets : Auto
  75. Add IO Buffers : YES
  76. Global Maximum Fanout : 100000
  77. Add Generic Clock Buffer(BUFG) : 32
  78. Register Duplication : YES
  79. Slice Packing : YES
  80. Optimize Instantiated Primitives : NO
  81. Use Clock Enable : Auto
  82. Use Synchronous Set : Auto
  83. Use Synchronous Reset : Auto
  84. Pack IO Registers into IOBs : Auto
  85. Equivalent register Removal : YES
  86.  
  87. ---- General Options
  88. Optimization Goal : Speed
  89. Optimization Effort : 2
  90. Power Reduction : NO
  91. Keep Hierarchy : No
  92. Netlist Hierarchy : As_Optimized
  93. RTL Output : Yes
  94. Global Optimization : AllClockNets
  95. Read Cores : YES
  96. Write Timing Constraints : NO
  97. Cross Clock Analysis : NO
  98. Hierarchy Separator : /
  99. Bus Delimiter : <>
  100. Case Specifier : Maintain
  101. Slice Utilization Ratio : 100
  102. BRAM Utilization Ratio : 100
  103. DSP48 Utilization Ratio : 100
  104. Verilog 2001 : YES
  105. Auto BRAM Packing : NO
  106. Slice Utilization Ratio Delta : 5
  107.  
  108. =========================================================================
  109.  
  110.  
  111. =========================================================================
  112. * HDL Compilation *
  113. =========================================================================
  114. Compiling vhdl file "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" in Library work.
  115. Entity <vedic_div32> compiled.
  116. Entity <vedic_div32> (Architecture <rtl>) compiled.
  117.  
  118. =========================================================================
  119. * Design Hierarchy Analysis *
  120. =========================================================================
  121. Analyzing hierarchy for entity <vedic_div32> in library <work> (architecture <rtl>).
  122.  
  123.  
  124. =========================================================================
  125. * HDL Analysis *
  126. =========================================================================
  127. Analyzing Entity <vedic_div32> in library <work> (Architecture <rtl>).
  128. WARNING:Xst:2096 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 84: Use of null array slice on signal <d_init_re_reg> is not supported.
  129. WARNING:Xst:2096 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 85: Use of null array slice on signal <init_reg.re_reg> is not supported.
  130. INFO:Xst:2679 - Register <d_init_quo_reg<31>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  131. INFO:Xst:2679 - Register <init_reg.re_reg<35>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  132. INFO:Xst:2679 - Register <init_reg.re_reg<34>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  133. INFO:Xst:2679 - Register <init_reg.re_reg<33>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  134. INFO:Xst:2679 - Register <init_reg.re_reg<32>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  135. INFO:Xst:2679 - Register <init_reg.re_reg<31>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  136. Entity <vedic_div32> analyzed. Unit <vedic_div32> generated.
  137.  
  138.  
  139. =========================================================================
  140. * HDL Synthesis *
  141. =========================================================================
  142.  
  143. Performing bidirectional port resolution...
  144.  
  145. Synthesizing Unit <vedic_div32>.
  146. Related source file is "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd".
  147. WARNING:Xst:653 - Signal <init_reg.quo> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
  148. WARNING:Xst:646 - Signal <d_state> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  149. WARNING:Xst:646 - Signal <d_re_tmp> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  150. WARNING:Xst:646 - Signal <d_re> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  151. WARNING:Xst:646 - Signal <d_main_re_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  152. WARNING:Xst:1780 - Signal <d_init_re_reg<31>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
  153. WARNING:Xst:646 - Signal <d_init_re_reg<30:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  154. WARNING:Xst:646 - Signal <d_init_quo_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  155. Found finite state machine <FSM_0> for signal <state>.
  156. -----------------------------------------------------------------------
  157. | States | 4 |
  158. | Transitions | 9 |
  159. | Inputs | 3 |
  160. | Outputs | 4 |
  161. | Clock | mclk1 (rising_edge) |
  162. | Reset | state$and0000 (positive) |
  163. | Reset type | synchronous |
  164. | Reset State | fin_state |
  165. | Power Up State | init_state |
  166. | Encoding | automatic |
  167. | Implementation | LUT |
  168. -----------------------------------------------------------------------
  169. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 123: The result of a 33x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  170. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  171. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  172. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  173. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  174. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  175. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 34x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  176. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  177. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 34x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  178. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 122: The result of a 33x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  179. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  180. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  181. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 207: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  182. Found 34x4-bit multiplier for signal <$mult0000> created at line 207.
  183. Found 34x5-bit multiplier for signal <$mult0001> created at line 207.
  184. Found 34x4-bit multiplier for signal <$mult0002> created at line 207.
  185. Found 34x5-bit multiplier for signal <$mult0003> created at line 207.
  186. Found 31-bit register for signal <b_n>.
  187. Found 5-bit register for signal <i>.
  188. Found 5-bit subtractor for signal <i$addsub0000> created at line 155.
  189. Found 32-bit register for signal <i_quo>.
  190. Found 32-bit register for signal <i_re>.
  191. Found 32-bit register for signal <init_reg.quo_reg>.
  192. Found 31-bit register for signal <init_reg.re_reg<30:0>>.
  193. Found 32-bit register for signal <k_reg.quo>.
  194. Found 36-bit register for signal <k_reg.re_reg>.
  195. Found 1-bit register for signal <k_reg.re_sign>.
  196. Found 32-bit register for signal <main_reg.quo>.
  197. Found 32-bit adder for signal <main_reg.quo$addsub0000> created at line 115.
  198. Found 32-bit subtractor for signal <main_reg.quo$addsub0001> created at line 117.
  199. Found 32-bit register for signal <main_reg.quo_reg>.
  200. Found 32-bit adder for signal <main_reg.quo_reg$addsub0000> created at line 134.
  201. Found 1-bit register for signal <main_reg.quo_sign>.
  202. Found 36-bit register for signal <main_reg.re_reg>.
  203. Found 36-bit adder for signal <main_reg.re_reg$addsub0000> created at line 139.
  204. Found 36-bit adder for signal <main_reg.re_reg$addsub0001> created at line 144.
  205. Found 1-bit xor2 for signal <main_reg.re_reg$cmp_ne0000> created at line 138.
  206. Found 1-bit register for signal <main_reg.re_sign>.
  207. Found 32-bit adder for signal <quo$addsub0000> created at line 241.
  208. Found 32-bit adder for signal <quo$addsub0001> created at line 241.
  209. Found 32-bit adder for signal <quo$addsub0002> created at line 241.
  210. Found 32-bit adder for signal <quo$addsub0003> created at line 241.
  211. Found 32-bit adder for signal <quo$addsub0004> created at line 241.
  212. Found 32-bit adder for signal <quo$addsub0005> created at line 241.
  213. Found 32-bit adder for signal <quo$addsub0006> created at line 241.
  214. Found 32-bit adder for signal <quo$addsub0007> created at line 241.
  215. Found 32-bit subtractor for signal <quo$addsub0008> created at line 241.
  216. Found 32-bit subtractor for signal <quo$addsub0009> created at line 241.
  217. Found 32-bit subtractor for signal <quo$addsub0010> created at line 241.
  218. Found 32-bit subtractor for signal <quo$addsub0011> created at line 241.
  219. Found 32-bit subtractor for signal <quo$addsub0012> created at line 241.
  220. Found 32-bit subtractor for signal <quo$addsub0013> created at line 241.
  221. Found 32-bit subtractor for signal <quo$addsub0014> created at line 241.
  222. Found 32-bit subtractor for signal <quo$addsub0015> created at line 241.
  223. Found 33-bit subtractor for signal <quo_reg_sub$sub0000> created at line 124.
  224. Found 33x32-bit multiplier for signal <quo_tmp$mult0001> created at line 122.
  225. Found 32-bit subtractor for signal <re$addsub0000> created at line 207.
  226. Found 32-bit subtractor for signal <re$addsub0001> created at line 207.
  227. Found 32-bit subtractor for signal <re$addsub0002> created at line 207.
  228. Found 32-bit subtractor for signal <re$addsub0003> created at line 207.
  229. Found 32-bit subtractor for signal <re$addsub0004> created at line 207.
  230. Found 32-bit subtractor for signal <re$addsub0005> created at line 207.
  231. Found 32-bit subtractor for signal <re$addsub0006> created at line 207.
  232. Found 32-bit subtractor for signal <re$addsub0007> created at line 207.
  233. Found 32-bit adder for signal <re$addsub0008> created at line 207.
  234. Found 32-bit adder for signal <re$addsub0009> created at line 207.
  235. Found 32-bit adder for signal <re$addsub0010> created at line 207.
  236. Found 32-bit adder for signal <re$addsub0011> created at line 207.
  237. Found 32-bit adder for signal <re$addsub0012> created at line 207.
  238. Found 32-bit adder for signal <re$addsub0013> created at line 207.
  239. Found 32-bit adder for signal <re$addsub0014> created at line 207.
  240. Found 32-bit adder for signal <re$addsub0015> created at line 207.
  241. Found 29-bit comparator greatequal for signal <re$cmp_ge0000> created at line 207.
  242. Found 32-bit comparator greatequal for signal <re$cmp_ge0001> created at line 207.
  243. Found 31-bit comparator greatequal for signal <re$cmp_ge0002> created at line 207.
  244. Found 32-bit comparator greatequal for signal <re$cmp_ge0003> created at line 207.
  245. Found 30-bit comparator greatequal for signal <re$cmp_ge0004> created at line 207.
  246. Found 32-bit comparator greatequal for signal <re$cmp_ge0005> created at line 207.
  247. Found 31-bit comparator greatequal for signal <re$cmp_ge0006> created at line 207.
  248. Found 32-bit comparator greatequal for signal <re$cmp_ge0007> created at line 207.
  249. Found 32-bit comparator greatequal for signal <re$cmp_ge0008> created at line 207.
  250. Found 32-bit comparator greatequal for signal <re$cmp_ge0009> created at line 207.
  251. Found 31-bit comparator greatequal for signal <re$cmp_ge0010> created at line 207.
  252. Found 32-bit comparator greatequal for signal <re$cmp_ge0011> created at line 207.
  253. Found 30-bit comparator greatequal for signal <re$cmp_ge0012> created at line 207.
  254. Found 32-bit comparator greatequal for signal <re$cmp_ge0013> created at line 207.
  255. Found 31-bit comparator greatequal for signal <re$cmp_ge0014> created at line 207.
  256. Found 32-bit comparator greatequal for signal <re$cmp_ge0015> created at line 207.
  257. Found 33x4-bit multiplier for signal <re$mult0005> created at line 207.
  258. Found 33x3-bit multiplier for signal <re$mult0006> created at line 207.
  259. Found 33x4-bit multiplier for signal <re$mult0007> created at line 207.
  260. Found 33x3-bit multiplier for signal <re$mult0008> created at line 207.
  261. Found 33x3-bit multiplier for signal <re$mult0010> created at line 207.
  262. Found 33x4-bit multiplier for signal <re$mult0011> created at line 207.
  263. Found 33x4-bit multiplier for signal <re$mult0012> created at line 207.
  264. Found 32-bit adder for signal <re$sub0000> created at line 207.
  265. Found 31-bit adder for signal <re$sub0001> created at line 207.
  266. Found 32-bit adder for signal <re$sub0002> created at line 207.
  267. Found 30-bit adder for signal <re$sub0003> created at line 207.
  268. Found 32-bit adder for signal <re$sub0004> created at line 207.
  269. Found 31-bit adder for signal <re$sub0005> created at line 207.
  270. Found 32-bit adder for signal <re$sub0006> created at line 207.
  271. Found 37-bit subtractor for signal <re_reg_sub$sub0000> created at line 125.
  272. Found 33x32-bit multiplier for signal <re_tmp$mult0001> created at line 123.
  273. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<30:1>> created at line 123.
  274. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<0>> created at line 123.
  275. Found 5-bit register for signal <shift_val>.
  276. Found 32-bit register for signal <tmp_quo_reg>.
  277. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_0$mux0000> created at line 110.
  278. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_1$mux0000> created at line 110.
  279. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_2$mux0000> created at line 110.
  280. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_3$mux0000> created at line 110.
  281. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_4$mux0000> created at line 110.
  282. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_5$mux0000> created at line 110.
  283. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_6$mux0000> created at line 110.
  284. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_7$mux0000> created at line 110.
  285. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_8$mux0000> created at line 110.
  286. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_shifted_0$mux0000> created at line 112.
  287. Found 36-bit adder for signal <v_re$addsub0000> created at line 196.
  288. Found 36-bit shifter arithmetic right for signal <v_re$shift0000> created at line 200.
  289. Found 1-bit 32-to-1 multiplexer for signal <v_reg.quo_reg_30$mux0000> created at line 120.
  290. Summary:
  291. inferred 1 Finite State Machine(s).
  292. inferred 371 D-type flip-flop(s).
  293. inferred 48 Adder/Subtractor(s).
  294. inferred 13 Multiplier(s).
  295. inferred 16 Comparator(s).
  296. inferred 42 Multiplexer(s).
  297. inferred 1 Combinational logic shifter(s).
  298. Unit <vedic_div32> synthesized.
  299.  
  300.  
  301. =========================================================================
  302. HDL Synthesis Report
  303.  
  304. Macro Statistics
  305. # Multipliers : 13
  306. 33x3-bit multiplier : 3
  307. 33x32-bit multiplier : 2
  308. 33x4-bit multiplier : 4
  309. 34x4-bit multiplier : 2
  310. 34x5-bit multiplier : 2
  311. # Adders/Subtractors : 48
  312. 30-bit adder : 1
  313. 31-bit adder : 2
  314. 32-bit adder : 22
  315. 32-bit subtractor : 17
  316. 33-bit subtractor : 1
  317. 36-bit adder : 3
  318. 37-bit subtractor : 1
  319. 5-bit subtractor : 1
  320. # Registers : 108
  321. 1-bit register : 98
  322. 31-bit register : 1
  323. 32-bit register : 5
  324. 36-bit register : 2
  325. 5-bit register : 2
  326. # Comparators : 16
  327. 29-bit comparator greatequal : 1
  328. 30-bit comparator greatequal : 2
  329. 31-bit comparator greatequal : 4
  330. 32-bit comparator greatequal : 9
  331. # Multiplexers : 42
  332. 1-bit 31-to-1 multiplexer : 1
  333. 1-bit 32-to-1 multiplexer : 41
  334. # Logic shifters : 1
  335. 36-bit shifter arithmetic right : 1
  336. # Xors : 1
  337. 1-bit xor2 : 1
  338.  
  339. =========================================================================
  340.  
  341. =========================================================================
  342. * Advanced HDL Synthesis *
  343. =========================================================================
  344.  
  345. Analyzing FSM <FSM_0> for best encoding.
  346. Optimizing FSM <state/FSM> on signal <state[1:4]> with one-hot encoding.
  347. ------------------------
  348. State | Encoding
  349. ------------------------
  350. init_state | 0001
  351. main_state | 0100
  352. wait_state | 1000
  353. fin_state | 0010
  354. ------------------------
  355.  
  356. =========================================================================
  357. Advanced HDL Synthesis Report
  358.  
  359. Macro Statistics
  360. # FSMs : 1
  361. # Multipliers : 13
  362. 33x3-bit multiplier : 3
  363. 33x32-bit multiplier : 2
  364. 33x4-bit multiplier : 4
  365. 34x4-bit multiplier : 2
  366. 34x5-bit multiplier : 2
  367. # Adders/Subtractors : 48
  368. 30-bit adder : 1
  369. 31-bit adder : 2
  370. 32-bit adder : 22
  371. 32-bit subtractor : 17
  372. 33-bit subtractor : 1
  373. 36-bit adder : 3
  374. 37-bit subtractor : 1
  375. 5-bit subtractor : 1
  376. # Registers : 370
  377. Flip-Flops : 370
  378. # Comparators : 16
  379. 29-bit comparator greatequal : 1
  380. 30-bit comparator greatequal : 2
  381. 31-bit comparator greatequal : 4
  382. 32-bit comparator greatequal : 9
  383. # Multiplexers : 42
  384. 1-bit 31-to-1 multiplexer : 1
  385. 1-bit 32-to-1 multiplexer : 41
  386. # Logic shifters : 1
  387. 36-bit shifter arithmetic right : 1
  388. # Xors : 1
  389. 1-bit xor2 : 1
  390.  
  391. =========================================================================
  392.  
  393. =========================================================================
  394. * Low Level Synthesis *
  395. =========================================================================
  396. WARNING:Xst:2677 - Node <Mmult_re_tmp_mult00013> of sequential type is unconnected in block <vedic_div32>.
  397. WARNING:Xst:2677 - Node <Mmult_quo_tmp_mult00013> of sequential type is unconnected in block <vedic_div32>.
  398.  
  399. Optimizing unit <vedic_div32> ...
  400.  
  401. Mapping all equations...
  402. Building and optimizing final netlist ...
  403. Found area constraint ratio of 100 (+ 5) on block vedic_div32, actual ratio is 23.
  404. FlipFlop i_1 has been replicated 1 time(s)
  405.  
  406. Final Macro Processing ...
  407.  
  408. =========================================================================
  409. Final Register Report
  410.  
  411. Macro Statistics
  412. # Registers : 374
  413. Flip-Flops : 374
  414.  
  415. =========================================================================
  416.  
  417. =========================================================================
  418. * Partition Report *
  419. =========================================================================
  420.  
  421. Partition Implementation Status
  422. -------------------------------
  423.  
  424. No Partitions were found in this design.
  425.  
  426. -------------------------------
  427.  
  428. =========================================================================
  429. * Final Report *
  430. =========================================================================
  431. Final Results
  432. RTL Top Level Output File Name : vedic_div32.ngr
  433. Top Level Output File Name : vedic_div32
  434. Output Format : NGC
  435. Optimization Goal : Speed
  436. Keep Hierarchy : No
  437.  
  438. Design Statistics
  439. # IOs : 130
  440.  
  441. Cell Usage :
  442. # BELS : 8946
  443. # GND : 1
  444. # INV : 530
  445. # LUT1 : 258
  446. # LUT2 : 1083
  447. # LUT3 : 312
  448. # LUT4 : 717
  449. # LUT5 : 396
  450. # LUT6 : 1516
  451. # MUXCY : 2092
  452. # MUXF7 : 124
  453. # VCC : 1
  454. # XORCY : 1916
  455. # FlipFlops/Latches : 374
  456. # FD : 184
  457. # FDE : 136
  458. # FDR : 2
  459. # FDRE : 35
  460. # FDRSE : 1
  461. # FDS : 16
  462. # Clock Buffers : 1
  463. # BUFGP : 1
  464. # IO Buffers : 129
  465. # IBUF : 65
  466. # OBUF : 64
  467. # DSPs : 6
  468. # DSP48E : 6
  469. =========================================================================
  470.  
  471. Device utilization summary:
  472. ---------------------------
  473.  
  474. Selected Device : 5vlx50tff1136-1
  475.  
  476.  
  477. Slice Logic Utilization:
  478. Number of Slice Registers: 374 out of 28800 1%
  479. Number of Slice LUTs: 4812 out of 28800 16%
  480. Number used as Logic: 4812 out of 28800 16%
  481.  
  482. Slice Logic Distribution:
  483. Number of LUT Flip Flop pairs used: 4889
  484. Number with an unused Flip Flop: 4515 out of 4889 92%
  485. Number with an unused LUT: 77 out of 4889 1%
  486. Number of fully used LUT-FF pairs: 297 out of 4889 6%
  487. Number of unique control sets: 42
  488.  
  489. IO Utilization:
  490. Number of IOs: 130
  491. Number of bonded IOBs: 130 out of 480 27%
  492.  
  493. Specific Feature Utilization:
  494. Number of BUFG/BUFGCTRLs: 1 out of 32 3%
  495. Number of DSP48Es: 6 out of 48 12%
  496.  
  497. ---------------------------
  498. Partition Resource Summary:
  499. ---------------------------
  500.  
  501. No Partitions were found in this design.
  502.  
  503. ---------------------------
  504.  
  505.  
  506. =========================================================================
  507. TIMING REPORT
  508.  
  509. NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
  510. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
  511. GENERATED AFTER PLACE-and-ROUTE.
  512.  
  513. Clock Information:
  514. ------------------
  515. -----------------------------------+------------------------+-------+
  516. Clock Signal | Clock buffer(FF name) | Load |
  517. -----------------------------------+------------------------+-------+
  518. mclk1 | BUFGP | 374 |
  519. -----------------------------------+------------------------+-------+
  520.  
  521. Asynchronous Control Signals Information:
  522. ----------------------------------------
  523. No asynchronous control signals found in this design
  524.  
  525. Timing Summary:
  526. ---------------
  527. Speed Grade: -1
  528.  
  529. Minimum period: 15.216ns (Maximum Frequency: 65.720MHz)
  530. Minimum input arrival time before clock: 10.356ns
  531. Maximum output required time after clock: 11.207ns
  532. Maximum combinational path delay: 15.455ns
  533.  
  534. Timing Detail:
  535. --------------
  536. All values displayed in nanoseconds (ns)
  537.  
  538. =========================================================================
  539. Timing constraint: Default period analysis for Clock 'mclk1'
  540. Clock period: 15.216ns (frequency: 65.720MHz)
  541. Total number of paths / destination ports: 9231017668 / 366
  542. -------------------------------------------------------------------------
  543. Delay: 15.216ns (Levels of Logic = 27)
  544. Source: b_n_14 (FF)
  545. Destination: main_reg.quo_reg_31 (FF)
  546. Source Clock: mclk1 rising
  547. Destination Clock: mclk1 rising
  548.  
  549. Data Path: b_n_14 to main_reg.quo_reg_31
  550. Gate Net
  551. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  552. ---------------------------------------- ------------
  553. FDE:C->Q 8 0.471 1.011 b_n_14 (b_n_14)
  554. LUT5:I0->O 1 0.094 0.973 quo_tmp_mux0000<13>77 (quo_tmp_mux0000<13>77)
  555. LUT5:I0->O 1 0.094 0.000 quo_tmp_mux0000<13>151_F (N580)
  556. MUXF7:I0->O 1 0.251 0.480 quo_tmp_mux0000<13>151 (quo_tmp_mux0000<13>151)
  557. LUT6:I5->O 1 0.094 0.000 quo_tmp_mux0000<13>179_G (N599)
  558. MUXF7:I1->O 1 0.254 0.336 quo_tmp_mux0000<13>179 (quo_tmp_mux0000<13>)
  559. DSP48E:A13->PCOUT20 1 3.832 0.000 Mmult_quo_tmp_mult0001 (Mmult_quo_tmp_mult0001_PCOUT_to_Mmult_quo_tmp_mult00011_PCIN_20)
  560. DSP48E:PCIN20->PCOUT12 1 2.013 0.000 Mmult_quo_tmp_mult00011 (Mmult_quo_tmp_mult00011_PCOUT_to_Mmult_quo_tmp_mult00012_PCIN_12)
  561. DSP48E:PCIN12->P0 1 1.816 0.480 Mmult_quo_tmp_mult00012 (quo_tmp_mult0001<17>)
  562. LUT6:I5->O 1 0.094 0.000 Msub_quo_reg_sub_sub0000_lut<17> (Msub_quo_reg_sub_sub0000_lut<17>)
  563. MUXCY:S->O 1 0.372 0.000 Msub_quo_reg_sub_sub0000_cy<17> (Msub_quo_reg_sub_sub0000_cy<17>)
  564. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<18> (Msub_quo_reg_sub_sub0000_cy<18>)
  565. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<19> (Msub_quo_reg_sub_sub0000_cy<19>)
  566. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<20> (Msub_quo_reg_sub_sub0000_cy<20>)
  567. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<21> (Msub_quo_reg_sub_sub0000_cy<21>)
  568. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<22> (Msub_quo_reg_sub_sub0000_cy<22>)
  569. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<23> (Msub_quo_reg_sub_sub0000_cy<23>)
  570. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<24> (Msub_quo_reg_sub_sub0000_cy<24>)
  571. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<25> (Msub_quo_reg_sub_sub0000_cy<25>)
  572. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<26> (Msub_quo_reg_sub_sub0000_cy<26>)
  573. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<27> (Msub_quo_reg_sub_sub0000_cy<27>)
  574. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<28> (Msub_quo_reg_sub_sub0000_cy<28>)
  575. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<29> (Msub_quo_reg_sub_sub0000_cy<29>)
  576. XORCY:CI->O 2 0.357 0.341 Msub_quo_reg_sub_sub0000_xor<30> (quo_reg_sub_sub0000<30>)
  577. INV:I->O 1 0.238 0.000 Madd_main_reg_quo_reg_not0000<30>1_INV_0 (Madd_main_reg_quo_reg_not0000<30>)
  578. MUXCY:S->O 0 0.372 0.000 Madd_main_reg.quo_reg_addsub0000_cy<30> (Madd_main_reg.quo_reg_addsub0000_cy<30>)
  579. XORCY:CI->O 1 0.357 0.480 Madd_main_reg.quo_reg_addsub0000_xor<31> (main_reg_quo_reg_addsub0000<31>)
  580. LUT3:I2->O 1 0.094 0.000 main_reg_quo_reg_mux0000<31>1 (main_reg_quo_reg_mux0000<31>)
  581. FD:D -0.018 main_reg.quo_reg_31
  582. ----------------------------------------
  583. Total 15.216ns (11.115ns logic, 4.101ns route)
  584. (73.0% logic, 27.0% route)
  585.  
  586. =========================================================================
  587. Timing constraint: Default OFFSET IN BEFORE for Clock 'mclk1'
  588. Total number of paths / destination ports: 8558 / 243
  589. -------------------------------------------------------------------------
  590. Offset: 10.356ns (Levels of Logic = 15)
  591. Source: divisor<2> (PAD)
  592. Destination: b_n_29 (FF)
  593. Destination Clock: mclk1 rising
  594.  
  595. Data Path: divisor<2> to b_n_29
  596. Gate Net
  597. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  598. ---------------------------------------- ------------
  599. IBUF:I->O 127 0.818 0.721 divisor_2_IBUF (divisor_2_IBUF)
  600. LUT2:I0->O 4 0.094 0.726 b_n_mux0000<1>11111 (N806)
  601. LUT6:I3->O 2 0.094 0.794 b_n_mux0000<1>182 (b_n_mux0000<1>182)
  602. LUT6:I2->O 1 0.094 0.000 b_n_mux0000<1>245_F (N632)
  603. MUXF7:I0->O 1 0.251 0.789 b_n_mux0000<1>245 (b_n_mux0000<1>245)
  604. LUT6:I2->O 1 0.094 0.480 b_n_mux0000<1>307 (b_n_mux0000<1>307)
  605. LUT6:I5->O 1 0.094 0.000 b_n_mux0000<1>461_SW01 (b_n_mux0000<1>461_SW0)
  606. MUXF7:I1->O 1 0.254 0.576 b_n_mux0000<1>461_SW0_f7 (N260)
  607. LUT6:I4->O 1 0.094 0.789 b_n_mux0000<1>461 (b_n_mux0000<1>461)
  608. LUT6:I2->O 1 0.094 0.710 b_n_mux0000<1>508 (b_n_mux0000<1>508)
  609. LUT5:I2->O 1 0.094 0.973 b_n_mux0000<1>587_SW1 (N518)
  610. LUT6:I1->O 1 0.094 0.480 b_n_mux0000<1>587 (b_n_mux0000<1>587)
  611. LUT6:I5->O 1 0.094 0.000 b_n_mux0000<1>692_SW02 (b_n_mux0000<1>692_SW01)
  612. MUXF7:I0->O 1 0.251 0.710 b_n_mux0000<1>692_SW0_f7 (N266)
  613. LUT6:I3->O 1 0.094 0.000 b_n_mux0000<1>692 (b_n_mux0000<1>)
  614. FDE:D -0.018 b_n_29
  615. ----------------------------------------
  616. Total 10.356ns (2.608ns logic, 7.748ns route)
  617. (25.2% logic, 74.8% route)
  618.  
  619. =========================================================================
  620. Timing constraint: Default OFFSET OUT AFTER for Clock 'mclk1'
  621. Total number of paths / destination ports: 154585 / 64
  622. -------------------------------------------------------------------------
  623. Offset: 11.207ns (Levels of Logic = 38)
  624. Source: i_re_1 (FF)
  625. Destination: re<30> (PAD)
  626. Source Clock: mclk1 rising
  627.  
  628. Data Path: i_re_1 to re<30>
  629. Gate Net
  630. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  631. ---------------------------------------- ------------
  632. FD:C->Q 39 0.471 0.705 i_re_1 (i_re_1)
  633. LUT2:I0->O 1 0.094 0.000 Madd_re_addsub0013_lut<1> (Madd_re_addsub0013_lut<1>)
  634. MUXCY:S->O 1 0.372 0.000 Madd_re_addsub0013_cy<1> (Madd_re_addsub0013_cy<1>)
  635. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<2> (Madd_re_addsub0013_cy<2>)
  636. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<3> (Madd_re_addsub0013_cy<3>)
  637. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<4> (Madd_re_addsub0013_cy<4>)
  638. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<5> (Madd_re_addsub0013_cy<5>)
  639. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<6> (Madd_re_addsub0013_cy<6>)
  640. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<7> (Madd_re_addsub0013_cy<7>)
  641. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<8> (Madd_re_addsub0013_cy<8>)
  642. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<9> (Madd_re_addsub0013_cy<9>)
  643. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<10> (Madd_re_addsub0013_cy<10>)
  644. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<11> (Madd_re_addsub0013_cy<11>)
  645. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<12> (Madd_re_addsub0013_cy<12>)
  646. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<13> (Madd_re_addsub0013_cy<13>)
  647. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<14> (Madd_re_addsub0013_cy<14>)
  648. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<15> (Madd_re_addsub0013_cy<15>)
  649. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<16> (Madd_re_addsub0013_cy<16>)
  650. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<17> (Madd_re_addsub0013_cy<17>)
  651. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<18> (Madd_re_addsub0013_cy<18>)
  652. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<19> (Madd_re_addsub0013_cy<19>)
  653. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<20> (Madd_re_addsub0013_cy<20>)
  654. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<21> (Madd_re_addsub0013_cy<21>)
  655. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<22> (Madd_re_addsub0013_cy<22>)
  656. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<23> (Madd_re_addsub0013_cy<23>)
  657. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<24> (Madd_re_addsub0013_cy<24>)
  658. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<25> (Madd_re_addsub0013_cy<25>)
  659. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<26> (Madd_re_addsub0013_cy<26>)
  660. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<27> (Madd_re_addsub0013_cy<27>)
  661. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<28> (Madd_re_addsub0013_cy<28>)
  662. MUXCY:CI->O 1 0.026 0.000 Madd_re_addsub0013_cy<29> (Madd_re_addsub0013_cy<29>)
  663. XORCY:CI->O 1 0.357 0.973 Madd_re_addsub0013_xor<30> (re_addsub0013<30>)
  664. LUT6:I1->O 1 0.094 0.710 re<30>66 (re<30>66)
  665. LUT6:I3->O 1 0.094 0.973 re<30>93 (re<30>93)
  666. LUT5:I0->O 1 0.094 0.789 re<30>125 (re<30>125)
  667. LUT6:I2->O 1 0.094 0.710 re<30>194_SW0 (N292)
  668. LUT6:I3->O 1 0.094 0.973 re<30>194 (re<30>194)
  669. LUT5:I0->O 1 0.094 0.336 re<30>233 (re_30_OBUF)
  670. OBUF:I->O 2.452 re_30_OBUF (re<30>)
  671. ----------------------------------------
  672. Total 11.207ns (5.038ns logic, 6.169ns route)
  673. (45.0% logic, 55.0% route)
  674.  
  675. =========================================================================
  676. Timing constraint: Default path analysis
  677. Total number of paths / destination ports: 82339987 / 64
  678. -------------------------------------------------------------------------
  679. Delay: 15.455ns (Levels of Logic = 45)
  680. Source: divisor<2> (PAD)
  681. Destination: quo<31> (PAD)
  682.  
  683. Data Path: divisor<2> to quo<31>
  684. Gate Net
  685. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  686. ---------------------------------------- ------------
  687. IBUF:I->O 127 0.818 0.721 divisor_2_IBUF (divisor_2_IBUF)
  688. LUT2:I0->O 1 0.094 0.000 Mmult_re_mult0012_Madd_lut<2> (Mmult_re_mult0012_Madd_lut<2>)
  689. MUXCY:S->O 1 0.372 0.000 Mmult_re_mult0012_Madd_cy<2> (Mmult_re_mult0012_Madd_cy<2>)
  690. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<3> (Mmult_re_mult0012_Madd_cy<3>)
  691. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<4> (Mmult_re_mult0012_Madd_cy<4>)
  692. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<5> (Mmult_re_mult0012_Madd_cy<5>)
  693. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<6> (Mmult_re_mult0012_Madd_cy<6>)
  694. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<7> (Mmult_re_mult0012_Madd_cy<7>)
  695. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<8> (Mmult_re_mult0012_Madd_cy<8>)
  696. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<9> (Mmult_re_mult0012_Madd_cy<9>)
  697. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<10> (Mmult_re_mult0012_Madd_cy<10>)
  698. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<11> (Mmult_re_mult0012_Madd_cy<11>)
  699. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<12> (Mmult_re_mult0012_Madd_cy<12>)
  700. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<13> (Mmult_re_mult0012_Madd_cy<13>)
  701. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<14> (Mmult_re_mult0012_Madd_cy<14>)
  702. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<15> (Mmult_re_mult0012_Madd_cy<15>)
  703. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<16> (Mmult_re_mult0012_Madd_cy<16>)
  704. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<17> (Mmult_re_mult0012_Madd_cy<17>)
  705. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<18> (Mmult_re_mult0012_Madd_cy<18>)
  706. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<19> (Mmult_re_mult0012_Madd_cy<19>)
  707. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<20> (Mmult_re_mult0012_Madd_cy<20>)
  708. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<21> (Mmult_re_mult0012_Madd_cy<21>)
  709. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<22> (Mmult_re_mult0012_Madd_cy<22>)
  710. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<23> (Mmult_re_mult0012_Madd_cy<23>)
  711. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<24> (Mmult_re_mult0012_Madd_cy<24>)
  712. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<25> (Mmult_re_mult0012_Madd_cy<25>)
  713. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<26> (Mmult_re_mult0012_Madd_cy<26>)
  714. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<27> (Mmult_re_mult0012_Madd_cy<27>)
  715. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<28> (Mmult_re_mult0012_Madd_cy<28>)
  716. XORCY:CI->O 1 0.357 0.576 Mmult_re_mult0012_Madd_xor<29> (Mmult_re_mult0012_Madd_29)
  717. LUT2:I0->O 1 0.094 0.000 Mmult_re_mult0012_Madd1_lut<29> (Mmult_re_mult0012_Madd1_lut<29>)
  718. MUXCY:S->O 1 0.372 0.000 Mmult_re_mult0012_Madd1_cy<29> (Mmult_re_mult0012_Madd1_cy<29>)
  719. XORCY:CI->O 1 0.357 0.336 Mmult_re_mult0012_Madd1_xor<30> (re_mult0012<30>)
  720. INV:I->O 1 0.238 0.000 Madd_re_not0006<30>1_INV_0 (Madd_re_not0006<30>)
  721. MUXCY:S->O 0 0.372 0.000 Madd_re_sub0006_cy<30> (Madd_re_sub0006_cy<30>)
  722. XORCY:CI->O 2 0.357 0.794 Madd_re_sub0006_xor<31> (re_sub0006<31>)
  723. LUT4:I0->O 0 0.094 0.000 Mcompar_re_cmp_ge0015_lutdi15 (Mcompar_re_cmp_ge0015_lutdi15)
  724. MUXCY:DI->O 8 0.590 0.518 Mcompar_re_cmp_ge0015_cy<15> (re_cmp_ge0015)
  725. LUT4:I3->O 61 0.094 0.922 quo<2>1111 (N656)
  726. LUT6:I2->O 1 0.094 0.973 re<9>93 (re<9>93)
  727. LUT5:I0->O 1 0.094 0.789 re<9>125 (re<9>125)
  728. LUT6:I2->O 1 0.094 0.710 re<9>194_SW0 (N278)
  729. LUT6:I3->O 1 0.094 0.973 re<9>194 (re<9>194)
  730. LUT5:I0->O 1 0.094 0.336 re<9>233 (re_9_OBUF)
  731. OBUF:I->O 2.452 re_9_OBUF (re<9>)
  732. ----------------------------------------
  733. Total 15.455ns (7.807ns logic, 7.648ns route)
  734. (50.5% logic, 49.5% route)
  735.  
  736. =========================================================================
  737.  
  738.  
  739. Total REAL time to Xst completion: 2155.00 secs
  740. Total CPU time to Xst completion: 2136.24 secs
  741.  
  742. -->
  743.  
  744.  
  745. Total memory usage is 910484 kilobytes
  746.  
  747. Number of errors : 0 ( 0 filtered)
  748. Number of warnings : 25 ( 0 filtered)
  749. Number of infos : 6 ( 0 filtered)
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