DNOLAB_4_9

--NOT
-----------------------------------------------------------
Library IEEE;
Use IEEE.STD_LOGIC_1164.all;
entity N is
port (
    a1: in STD_LOGIC;
    b1: out STD_LOGIC);
end N;

architecture archNOT of N is
begin
    b1 <= not a1 after 1 ns;
end archNOT;
--NA2
-----------------------------------------------------------
Library IEEE;
Use IEEE.STD_LOGIC_1164.all;
entity NA2 is
port (
    a1, a2: in STD_LOGIC;
    b1: out STD_LOGIC);
end NA2;

architecture archNA2 of NA2 is
begin
    b1 <= not(a1 and a2) after 2 ns;
end archNA2;
--NO3
-----------------------------------------------------------
Library IEEE;
Use IEEE.STD_LOGIC_1164.all;
entity NO3 is
port (
    a1, a2, a3: in STD_LOGIC;
    b1: out STD_LOGIC);
end NO3;

architecture archNO3 of NO3 is
begin
    b1 <= not(a1 or a2 or a3) after 4 ns;
end archNO3;
--NAO22
-----------------------------------------------------------
Library IEEE;
Use IEEE.STD_LOGIC_1164.all;
entity NAO22 is
port (
    a1, a2, a3, a4: in STD_LOGIC;
    b1: out STD_LOGIC);
end NAO22;

architecture archNAO22 of NAO22 is
begin
    b1 <= not((a1 or a2) and (a3 or a4)) after 3 ns;
end archNAO22;
--NO3A2
-----------------------------------------------------------
Library IEEE;
Use IEEE.STD_LOGIC_1164.all;
entity NO3A2 is
port (
    a1, a2, a3, a4: in STD_LOGIC;
    b1: out STD_LOGIC);
end NO3A2;

architecture archNO3A2 of NO3A2 is
begin
    b1 <= not(a1 or a2 or (a4 and a3)) after 5 ns;
end archNO3A2;
--NAOA2
-----------------------------------------------------------
Library IEEE;
Use IEEE.STD_LOGIC_1164.all;
entity NAOA2 is
port (
    a1, a2, a3, a4: in STD_LOGIC;
    b1: out STD_LOGIC);
end NAOA2;

architecture archNAOA2 of NAOA2 is
begin
    b1 <= not(a2 and (a2 or (a3 and a4))) after 4 ns;
end archNAOA2;
--NOA2
-----------------------------------------------------------
Library IEEE;
Use IEEE.STD_LOGIC_1164.all;
entity NOA2 is
port (
    a1, a2, a3: in STD_LOGIC;
    b1: out STD_LOGIC);
end NOA2;

architecture archNOA2 of NOA2 is
begin
    b1 <= not(a1 or (a2 and a3)) after 3 ns;
end archNOA2;
--NOAO2
-----------------------------------------------------------
Library IEEE;
Use IEEE.STD_LOGIC_1164.all;
entity NOAO2 is
port (
    a1, a2, a3, a4: in STD_LOGIC;
    b1: out STD_LOGIC);
end NOAO2;

architecture archNOAO2 of NOAO2 is
begin
    b1 <= not(a1 or (a2 and (a3 or a4))) after 4 ns;
end archNOAO2;
--NAO3
-----------------------------------------------------------
Library IEEE;
Use IEEE.STD_LOGIC_1164.all;
entity NAO3 is
port (
    a1, a2, a3, a4: in STD_LOGIC;
    b1: out STD_LOGIC);
end NAO3;

architecture archNAO3 of NAO3 is
begin
    b1 <= not(a1 and (a2 or a3 or a4)) after 5 ns;
end archNAO3;
--------------------------------------------------
Library IEEE;
USE IEEE.STD_LOGIC_1164.all;

entity VAR1 is
port(x1, x2, x3, x4: in STD_LOGIC;
     y2, y4, y1, y5: out STD_LOGIC);
end VAR1;

architecture archVAR1 of VAR1 is

component N
port(a1: in STD_LOGIC;
     b1: out STD_LOGIC);
end component;

component NA2
port(a1, a2: in STD_LOGIC;
     b1: out STD_LOGIC);
end component;

component NO3
port(a1, a2, a3: in STD_LOGIC;
     b1: out STD_LOGIC);
end component;

component NAO22
port(a1, a2, a3, a4: in STD_LOGIC;
     b1: out STD_LOGIC);
end component;

component NO3A2
port(a1, a2, a3, a4: in STD_LOGIC;
     b1: out STD_LOGIC);
end component;

component NAOA2
port(a1, a2, a3, a4: in STD_LOGIC;
     b1: out STD_LOGIC);
end component;

component NOA2
port(a1, a2, a3: in STD_LOGIC;
     b1: out STD_LOGIC);
end component;

component NOAO2
port(a1, a2, a3, a4: in STD_LOGIC;
     b1: out STD_LOGIC);
end component;

component NAO3
port(a1, a2, a3, a4: in STD_LOGIC;
     b1: out STD_LOGIC);
end component;
--------------------------------------------------
signal za1,za2,za3,zb1,zb2,zb3,zb4,zc1,zc2,zc3,zc4,zc5,zd1,zd2,zd3: STD_LOGIC;

begin
A_1:N port map(x1,za1);
A_2:NA2 port map(x1,x4,za2);
A_3:N port map(x2,za3);
B_1:NO3 port map(x2,x4,za1,zb1);
B_2:NAO22 port map(x4,x1,x2,za2,zb2);
B_3:N port map(x3,zb3);
B_4:NO3A2 port map(x3,za3,x1,x4,zb4);
C_1:NAOA2 port map(zb3,zb1,za1,zd1,zc1);
C_2:NO3 port map(za3,zb3,x4,zc2);
C_3:N port map(x4,zc3);
C_4:NOA2 port map(zb4,x3,zb2,zc4);
C_5:N port map(zd3,zc5);
D_1:NOAO2 port map(zc3,x2,zb3,za1,zd1);
D_3:N port map(zc4,zd3);
D_4:NAO3 port map(zc1,zc2,x1,zc5,y1);
y2 <= zd1;
y4 <= zc2;
y5 <= zd3;
end archVAR1;
---------------------------------------------------
Library IEEE;
USE IEEE.STD_LOGIC_1164.all;

entity test is
end test;

architecture newTEST of test is
component VAR1
port(x1,x2,x3,x4: in STD_LOGIC;
     y2,y4,y1,y5: out STD_LOGIC);
end component;

signal x1,x2,x3,x4,y2,y4,y1,y5: STD_LOGIC;
begin
x1 <= '1','0' after 200 ns,'1' after 300 ns,'0' after 400 ns,'1' after 600 ns,'0' after 700 ns,'1' after 800 ns,'0' after 1000 ns,'1' after 1100 ns,'0' after 1300 ns;
x2 <= '1','0' after 100 ns,'1' after 400 ns,'0' after 600 ns,'1' after 800 ns,'0' after 900 ns,'1' after 1000 ns,'0' after 1300 ns;
x3 <= '1','0' after 100 ns,'1' after 300 ns,'0' after 400 ns,'1' after 500 ns,'0' after 600 ns,'1' after 900 ns,'0' after 1200 ns,'1' after 1300 ns;
x4 <= '0','1' after 100 ns,'0' after 300 ns,'1' after 400 ns,'0' after 500 ns,'1' after 800 ns,'0' after 1200 ns,'1' after 1300 ns;

ALLVAR1: VAR1 port map(x1,x2,x3,x4,y2,y4,y1,y5);
end newTEST;