mux_unidades

library ieee;
use ieee.std_logic_1164.all;

entity mux_0 is
    port (
        bcd0 : in std_logic_vector(3 downto 0);
        SW9  : in std_logic_vector(1 downto 0);
        UD   : out std_logic_vector(3 downto 0)
    );
end mux_0;

architecture dataflow of mux_0 is

begin

    process (SW9, bcd0) is

    begin

        case SW9 is
            when "00" => UD <= "0010";
            when "01" => UD <= bcd0;
            when others => UD <= (others => '0');
        end case;

    end process;

end dataflow;