zmatt

BeagleBone AI video inputs

Jun 12th, 2020 (edited)
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  1. Summary of video interfaces/formats supported:
  2.  
  3. 8-bit interface:
  4. - YUV422 (interleaved) with discrete sync or embedded sync (BT.656).
  5. - pixel- or line-multiplexed multi-video stream with embedded sync.
  6.  
  7. 16-bit interface:
  8. - RGB565 with discrete sync. Can alternatively use d3-d7 + d10-d15 + d19-d23.
  9. - YUV422 (separate luma/chroma) with discrete sync or embedded sync (BT.1120).
  10.  
  11. 24-bit interface:
  12. - RGB888 or YUV444 with discrete sync or embedded sync (BT.1120).
  13.  
  14. "Embedded sync" means synchronization markers are embedded in the video data stream,
  15. similar to the sync pulses embedded in analog composite video signals, and therefore the
  16. interface only uses clk + data lines, no separate synchronization signals.
  17.  
  18. "Discrete sync" means separate vsync/hsync/de/fld signals (or some subset thereof) are
  19. used to synchronize to the video timing. To use discrete sync, the video input port
  20. requires at least vsync+hsync or vsync+de. Interleaved video additionally needs either
  21. fld or vsync+hsync (in the latter case the field identification is determined by timing
  22. of vsync relative to hsync, same as in analog video).
  23.  
  24.  
  25. ======== vin4a (VIP2 slice 1 input A) ========
  26.  
  27. It's a mix of different iosets so timing is probably degraded (unless you manage
  28. to tune the iodelay manually), which will limit the max pixel clock supported.
  29.  
  30. Nearly a full-featured input, except only 23 of the 24 data signals are available;
  31. you can pick any two of { d7, d8, d17 } but not all three.
  32.  
  33. For 24-bit RGB or YUV444, sacrificing d8 is probably the best option, since it is the
  34. least significant bit of one channel. By default it will be green (for RGB) or Cb
  35. (for YUV), but you can use the "repacker" to swap channels and e.g. make d8 the least
  36. significant bit of the _blue_ channel instead to minimize the visual impact of its loss.
  37.  
  38. For 16-bit RGB or YUV422 input on d0-d15, you don't need d17 so there's no problem.
  39. RGB565 can also be provided on d3-d7 (blue) + d10-d15 (green) + d19-d23 (red), i.e. the
  40. most significant bits of RGB888. In this case neither d8 nor d17 is used.
  41.  
  42. P9.22 clk
  43.  
  44. P9.24 vsync
  45. P9.26 hsync
  46. P9.41 de
  47.  
  48. P9.12 d0 also available on P9.19
  49. P9.11 d1 also available on P9.20 and P9.27
  50. P8.17 d2
  51. P8.27 d3
  52. P8.28 d4 or fld
  53. P8.29 d5
  54. P8.30 d6
  55. P8.46 d7 or d17
  56. P8.37 d8 or d17
  57. P8.38 d9
  58. P8.36 d10
  59. P8.34 d11 same pin as vin2b vsync, see comments there
  60. P8.35 d12
  61. P8.33 d13
  62. P8.31 d14
  63. P8.32 d15
  64. P8.45 d16
  65. - d17 see d7/d8 above
  66. P8.43 d18
  67. P8.44 d19
  68. P8.41 d20
  69. P8.42 d21
  70. P8.39 d22
  71. P8.40 d23
  72.  
  73.  
  74. ======== vin6a (VIP3 slice 1 input A) ========
  75.  
  76. All pins belong to a single ioset.
  77.  
  78. Although only d8-d15 are available for this input, it should be possible to use the
  79. "repacker" to swap those with d0-d7, hopefully allowing this port to be used for any
  80. of the supported 8-bit interfaces.
  81.  
  82. P8.09 clk
  83.  
  84. P9.18 vsync
  85. P9.17 hsync
  86.  
  87. P8.08 d8
  88. P8.07 d9
  89. P8.10 d10
  90. P9.42 d11
  91. P9.28 d12
  92. P9.30 d13
  93. P9.29 d14
  94. P9.31 d15
  95.  
  96.  
  97. ======== vin2b (VIP1 slice 1 input B) ========
  98.  
  99. All pins belong to a single ioset, except for vsync.
  100.  
  101. This interface is not ideal for use with discrete sync:
  102. - it has vsync + de instead of vsync + hsync (hence no support for interleaved video).
  103. - the vsync signal belongs to a different ioset than the other signals.
  104. - vsync is on the same expansion header pin as vin4a d11, and stealing that pin from
  105. it would pretty much limit vin4a to 8-bit input.
  106.  
  107. It would have been nice if VIP supported DE-only discrete sync, but afaict it does not.
  108.  
  109. This port is still fine for video with embedded sync (BT.656) of course.
  110.  
  111. P8.04 clk
  112.  
  113. P8.34 vsync see comments above
  114. P8.03 de
  115.  
  116. P8.22 d0
  117. P8.23 d1
  118. P8.06 d2
  119. P8.05 d3
  120. P8.24 d4
  121. P8.25 d5
  122. P8.20 d6
  123. P8.21 d7
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