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- From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
- From: Reilly Brogan <reilly@reillybrogan.com>
- Date: Thu, 30 Nov 2023 16:26:27 -0600
- Subject: [PATCH] Reapply "drm/amd/display: disable SubVP + DRR to prevent
- underflow"
- This reverts commit f38129bb081758176dd78304faaee95007fb8838.
- Causes flickering on my AMD 7900xtx GPU. See https://gitlab.freedesktop.org/drm/amd/-/issues/2904
- ---
- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++++
- drivers/gpu/drm/amd/display/dc/dc.h | 1 +
- drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 4 ++++
- drivers/gpu/drm/amd/include/amd_shared.h | 1 +
- 4 files changed, 11 insertions(+)
- diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- index affc628004ff..7f9ce33340b9 100644
- --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
- @@ -1664,6 +1664,11 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
- if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
- init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
- + /* Disable SubVP + DRR config by default */
- + init_data.flags.disable_subvp_drr = true;
- + if (amdgpu_dc_feature_mask & DC_ENABLE_SUBVP_DRR)
- + init_data.flags.disable_subvp_drr = false;
- +
- init_data.flags.seamless_boot_edp_requested = false;
- if (amdgpu_device_seamless_boot_supported(adev)) {
- diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
- index 2cafd644baff..555d951a5fef 100644
- --- a/drivers/gpu/drm/amd/display/dc/dc.h
- +++ b/drivers/gpu/drm/amd/display/dc/dc.h
- @@ -428,6 +428,7 @@ struct dc_config {
- uint8_t force_bios_fixed_vs;
- int sdpif_request_limit_words_per_umc;
- bool use_old_fixed_vs_sequence;
- + bool disable_subvp_drr;
- bool dc_mode_clk_limit_support;
- bool EnableMinDispClkODM;
- bool enable_auto_dpm_test_logs;
- diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
- index 92e2ddc9ab7e..a6cceca78a7b 100644
- --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
- +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
- @@ -796,6 +796,10 @@ static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context)
- int16_t stretched_drr_us = 0;
- int16_t drr_stretched_vblank_us = 0;
- int16_t max_vblank_mallregion = 0;
- + const struct dc_config *config = &dc->config;
- +
- + if (config->disable_subvp_drr)
- + return false;
- // Find SubVP pipe
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
- index 579977f6ad52..b758882b9343 100644
- --- a/drivers/gpu/drm/amd/include/amd_shared.h
- +++ b/drivers/gpu/drm/amd/include/amd_shared.h
- @@ -244,6 +244,7 @@ enum DC_FEATURE_MASK {
- DC_DISABLE_LTTPR_DP2_0 = (1 << 6), //0x40, disabled by default
- DC_PSR_ALLOW_SMU_OPT = (1 << 7), //0x80, disabled by default
- DC_PSR_ALLOW_MULTI_DISP_OPT = (1 << 8), //0x100, disabled by default
- + DC_ENABLE_SUBVP_DRR = (1 << 9), // 0x200, disabled by default
- };
- enum DC_DEBUG_MASK {
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