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cofyye

MUX 2 TO 1

Apr 30th, 2023
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VHDL 1.12 KB | Source Code | 0 0
  1. -- design.vhd
  2.  
  3. library IEEE;
  4. use IEEE.std_logic_1164.all;
  5.  
  6. entity mux2to1 is
  7.     port(A : in bit_vector(1 downto 0);
  8.          Sel : in std_logic_vector(1 downto 0);
  9.          F : out bit);
  10. end entity;
  11.  
  12. architecture mux2to1_arch of mux2to1 is
  13. begin
  14.     process(A, Sel)
  15.     begin
  16.         if(Sel = "01") then
  17.             F <= A(0);
  18.         elsif(Sel = "10") then
  19.             F <= A(1);
  20.         else
  21.             F <= '0';
  22.         end if;
  23.     end process;
  24. end architecture mux2to1_arch;
  25.  
  26. -- testbench.vhd
  27.  
  28. library IEEE;
  29. use IEEE.std_logic_1164.all;
  30.  
  31. entity mux2to1_tb is
  32. end entity mux2to1_tb;
  33.  
  34. architecture mux2to1_tb_arch of mux2to1_tb is
  35.     signal A : bit_vector(1 downto 0);
  36.     signal Sel : std_logic_vector(1 downto 0);
  37.     signal F : bit;
  38. begin
  39.     DUT1 : entity work.mux2to1(mux2to1_arch)
  40.            port map(A, Sel, F);
  41.     STIMULUS : process
  42.     begin
  43.         A <= "01"; wait for 10ns;
  44.         Sel <= "00"; wait for 10ns;
  45.         Sel <= "01"; wait for 10ns;
  46.         Sel <= "10"; wait for 10ns;
  47.         Sel <= "11"; wait for 10ns;
  48.         Sel <= "XX"; wait for 10ns;
  49.     end process STIMULUS;
  50. end architecture mux2to1_tb_arch;
  51.  
Tags: VHDL
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