library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity trans is
    Port ( wej : in  STD_LOGIC_VECTOR(3 downto 0);
           wyj : out  STD_LOGIC_VECTOR(6 downto 0));
end trans;

architecture Behavioral of trans is

begin
with wej select
wyj <= "0001100" when "0000",
         "0101111" when "0001",
         "0100011" when "0010",
         "0010010" when "0011",
         "0000111" when "0100",
         "0000110" when "0101",
         "1110111" when "0110",
         "0100100" when "0111",
         "0001000" when "1000",
         "0100001" when "1001",
         "0001000" when "1010",
         "0101011" when "1011",
         "1111011" when "1100",
         "0000110" when "1101",
         "1110111" when "1110",
         "1110111" when "1111",
         "0000000" when others;
end Behavioral;