freq_divider

`timescale 1ns / 1ps

module freq_divider(
    input clk,
    output reg clk_out = 0
);

reg[4:0] count = 3'b000;

always @(posedge clk) begin
        if (count == 3'b100) begin
            clk_out <= ~clk_out;
            count <= 0;
        end
        else
        count <= count + 1;
end
endmodule