Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- -- design.vhd
- library IEEE;
- use IEEE.std_logic_1164.all;
- entity comparator is
- port(A, B : in std_logic_vector(3 downto 0);
- F : out std_logic_vector(3 downto 0));
- end entity comparator;
- architecture comparator_arch of comparator is
- begin
- process(A, B)
- begin
- if(A > B) then
- F <= A;
- elsif(A < B) then
- F <= B;
- else
- F <= A;
- end if;
- end process;
- end architecture comparator_arch;
- -- testbench.vhd
- library IEEE;
- use IEEE.std_logic_1164.all;
- entity comparator_tb is
- end entity comparator_tb;
- architecture comparator_tb_arch of comparator_tb is
- signal A, B, F : std_logic_vector(3 downto 0);
- begin
- DUT1 : entity work.comparator(comparator_arch)
- port map(A, B, F);
- STIMULUS : process
- begin
- A <= "0001"; B <= "0100"; wait for 10ns;
- A <= "0101"; B <= "0101"; wait for 10ns;
- A <= "0101"; B <= "0100"; wait for 10ns;
- A <= "1000"; B <= "1100"; wait for 10ns;
- A <= "0000"; B <= "0110"; wait for 10ns;
- A <= "1001"; B <= "0101"; wait for 10ns;
- A <= "0101"; B <= "0111"; wait for 10ns;
- end process STIMULUS;
- end architecture comparator_tb_arch;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement