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cofyye

COMPARATOR

Apr 30th, 2023
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VHDL 1.20 KB | Source Code | 0 0
  1. -- design.vhd
  2.  
  3. library IEEE;
  4. use IEEE.std_logic_1164.all;
  5.  
  6. entity comparator is
  7.     port(A, B : in std_logic_vector(3 downto 0);
  8.          F : out std_logic_vector(3 downto 0));
  9. end entity comparator;
  10.  
  11. architecture comparator_arch of comparator is
  12. begin
  13.     process(A, B)
  14.     begin
  15.         if(A > B) then
  16.             F <= A;
  17.         elsif(A < B) then
  18.             F <= B;
  19.         else
  20.             F <= A;
  21.         end if;
  22.     end process;
  23. end architecture comparator_arch;
  24.    
  25. -- testbench.vhd
  26.  
  27. library IEEE;
  28. use IEEE.std_logic_1164.all;
  29.  
  30. entity comparator_tb is
  31. end entity comparator_tb;
  32.  
  33. architecture comparator_tb_arch of comparator_tb is
  34.     signal A, B, F : std_logic_vector(3 downto 0);
  35. begin
  36.     DUT1 : entity work.comparator(comparator_arch)
  37.            port map(A, B, F);
  38.     STIMULUS : process
  39.     begin
  40.         A <= "0001"; B <= "0100"; wait for 10ns;
  41.         A <= "0101"; B <= "0101"; wait for 10ns;
  42.         A <= "0101"; B <= "0100"; wait for 10ns;
  43.         A <= "1000"; B <= "1100"; wait for 10ns;
  44.         A <= "0000"; B <= "0110"; wait for 10ns;
  45.         A <= "1001"; B <= "0101"; wait for 10ns;
  46.         A <= "0101"; B <= "0111"; wait for 10ns;
  47.     end process STIMULUS;
  48. end architecture comparator_tb_arch;
Tags: VHDL
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