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vedic_div32.syr.8d9a545505e597119032748a96c0b36ed76b0015

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May 9th, 2015
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  1. Release 14.4 - xst P.49d (lin64)
  2. Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
  3. -->
  4. Parameter TMPDIR set to xst/projnav.tmp
  5.  
  6.  
  7. Total REAL time to Xst completion: 0.00 secs
  8. Total CPU time to Xst completion: 0.07 secs
  9.  
  10. -->
  11. Parameter xsthdpdir set to xst
  12.  
  13.  
  14. Total REAL time to Xst completion: 0.00 secs
  15. Total CPU time to Xst completion: 0.07 secs
  16.  
  17. -->
  18. Reading design: vedic_div32.prj
  19.  
  20. TABLE OF CONTENTS
  21. 1) Synthesis Options Summary
  22. 2) HDL Compilation
  23. 3) Design Hierarchy Analysis
  24. 4) HDL Analysis
  25. 5) HDL Synthesis
  26. 5.1) HDL Synthesis Report
  27. 6) Advanced HDL Synthesis
  28. 6.1) Advanced HDL Synthesis Report
  29. 7) Low Level Synthesis
  30. 8) Partition Report
  31. 9) Final Report
  32. 9.1) Device utilization summary
  33. 9.2) Partition Resource Summary
  34. 9.3) TIMING REPORT
  35.  
  36.  
  37. =========================================================================
  38. * Synthesis Options Summary *
  39. =========================================================================
  40. ---- Source Parameters
  41. Input File Name : "vedic_div32.prj"
  42. Input Format : mixed
  43. Ignore Synthesis Constraint File : NO
  44.  
  45. ---- Target Parameters
  46. Output File Name : "vedic_div32"
  47. Output Format : NGC
  48. Target Device : xc5vlx50t-1-ff1136
  49.  
  50. ---- Source Options
  51. Top Module Name : vedic_div32
  52. Automatic FSM Extraction : YES
  53. FSM Encoding Algorithm : Auto
  54. Safe Implementation : No
  55. FSM Style : LUT
  56. RAM Extraction : Yes
  57. RAM Style : Auto
  58. ROM Extraction : Yes
  59. Mux Style : Auto
  60. Decoder Extraction : YES
  61. Priority Encoder Extraction : Yes
  62. Shift Register Extraction : YES
  63. Logical Shifter Extraction : YES
  64. XOR Collapsing : YES
  65. ROM Style : Auto
  66. Mux Extraction : Yes
  67. Resource Sharing : YES
  68. Asynchronous To Synchronous : NO
  69. Use DSP Block : Auto
  70. Automatic Register Balancing : No
  71.  
  72. ---- Target Options
  73. LUT Combining : Off
  74. Reduce Control Sets : Off
  75. Add IO Buffers : YES
  76. Global Maximum Fanout : 100000
  77. Add Generic Clock Buffer(BUFG) : 32
  78. Register Duplication : YES
  79. Slice Packing : YES
  80. Optimize Instantiated Primitives : NO
  81. Use Clock Enable : Auto
  82. Use Synchronous Set : Auto
  83. Use Synchronous Reset : Auto
  84. Pack IO Registers into IOBs : Auto
  85. Equivalent register Removal : YES
  86.  
  87. ---- General Options
  88. Optimization Goal : Speed
  89. Optimization Effort : 1
  90. Power Reduction : NO
  91. Keep Hierarchy : No
  92. Netlist Hierarchy : As_Optimized
  93. RTL Output : Yes
  94. Global Optimization : AllClockNets
  95. Read Cores : YES
  96. Write Timing Constraints : NO
  97. Cross Clock Analysis : NO
  98. Hierarchy Separator : /
  99. Bus Delimiter : <>
  100. Case Specifier : Maintain
  101. Slice Utilization Ratio : 100
  102. BRAM Utilization Ratio : 100
  103. DSP48 Utilization Ratio : 100
  104. Verilog 2001 : YES
  105. Auto BRAM Packing : NO
  106. Slice Utilization Ratio Delta : 5
  107.  
  108. =========================================================================
  109.  
  110.  
  111. =========================================================================
  112. * HDL Compilation *
  113. =========================================================================
  114. Compiling vhdl file "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" in Library work.
  115. Architecture rtl of Entity vedic_div32 is up to date.
  116.  
  117. =========================================================================
  118. * Design Hierarchy Analysis *
  119. =========================================================================
  120. Analyzing hierarchy for entity <vedic_div32> in library <work> (architecture <rtl>).
  121.  
  122.  
  123. =========================================================================
  124. * HDL Analysis *
  125. =========================================================================
  126. Analyzing Entity <vedic_div32> in library <work> (Architecture <rtl>).
  127. WARNING:Xst:2096 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 81: Use of null array slice on signal <d_init_re_reg> is not supported.
  128. INFO:Xst:2679 - Register <d_init_quo_reg<31>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  129. INFO:Xst:2679 - Register <init_reg.re_reg<35>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  130. INFO:Xst:2679 - Register <init_reg.re_reg<34>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  131. INFO:Xst:2679 - Register <init_reg.re_reg<33>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  132. INFO:Xst:2679 - Register <init_reg.re_reg<32>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  133. INFO:Xst:2679 - Register <init_reg.re_reg<31>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  134. INFO:Xst:2679 - Register <init_reg.re_reg<0>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  135. Entity <vedic_div32> analyzed. Unit <vedic_div32> generated.
  136.  
  137.  
  138. =========================================================================
  139. * HDL Synthesis *
  140. =========================================================================
  141.  
  142. Performing bidirectional port resolution...
  143.  
  144. Synthesizing Unit <vedic_div32>.
  145. Related source file is "/home/calros/enshu3-vedicdivider/vedic_div32.vhd".
  146. WARNING:Xst:653 - Signal <init_reg.quo> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
  147. WARNING:Xst:646 - Signal <d_state> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  148. WARNING:Xst:646 - Signal <d_re> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  149. WARNING:Xst:1780 - Signal <d_init_re_reg<31>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
  150. WARNING:Xst:646 - Signal <d_init_re_reg<30:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  151. WARNING:Xst:646 - Signal <d_init_quo_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  152. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  153. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  154. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  155. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  156. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  157. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  158. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  159. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  160. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  161. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  162. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  163. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  164. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  165. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  166. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  167. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  168. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  169. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  170. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  171. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  172. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  173. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  174. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  175. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  176. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  177. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  178. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  179. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  180. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  181. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  182. Found finite state machine <FSM_0> for signal <state>.
  183. -----------------------------------------------------------------------
  184. | States | 4 |
  185. | Transitions | 9 |
  186. | Inputs | 3 |
  187. | Outputs | 4 |
  188. | Clock | mclk1 (rising_edge) |
  189. | Reset | state$and0000 (positive) |
  190. | Reset type | synchronous |
  191. | Reset State | fin_state |
  192. | Power Up State | init_state |
  193. | Encoding | automatic |
  194. | Implementation | LUT |
  195. -----------------------------------------------------------------------
  196. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  197. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  198. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  199. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  200. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_8>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  201. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_10>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  202. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_9>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  203. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  204. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_12>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  205. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_13>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  206. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_14>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  207. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_15>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  208. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_20>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  209. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_16>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  210. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_21>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  211. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_22>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  212. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_17>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  213. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_18>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  214. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_23>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  215. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_19>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  216. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_24>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  217. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_25>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  218. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_30>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  219. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_26>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  220. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_27>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  221. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  222. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_28>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  223. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  224. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_29>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  225. WARNING:Xst:737 - Found 5-bit latch for signal <shift_val>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  226. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  227. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  228. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  229. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  230. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  231. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_8>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  232. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_9>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  233. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_10>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  234. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  235. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_12>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  236. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_13>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  237. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_14>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  238. WARNING:Xst:737 - Found 31-bit latch for signal <b_n>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  239. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_15>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  240. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_20>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  241. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_16>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  242. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_21>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  243. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_17>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  244. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_22>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  245. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_23>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  246. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_18>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  247. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_19>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  248. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_24>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  249. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_25>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  250. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_30>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  251. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_26>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  252. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_31>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  253. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_27>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  254. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_28>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  255. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_29>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  256. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  257. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  258. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  259. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  260. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 126: The result of a 33x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  261. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  262. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  263. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  264. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  265. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  266. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  267. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  268. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 34x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  269. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 120: The result of a 33x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  270. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  271. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  272. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  273. WARNING:Xst:643 - "/home/calros/enshu3-vedicdivider/vedic_div32.vhd" line 207: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  274. Found 34x4-bit multiplier for signal <$mult0000> created at line 207.
  275. Found 34x5-bit multiplier for signal <$mult0001> created at line 207.
  276. Found 34x5-bit multiplier for signal <$mult0002> created at line 207.
  277. Found 34x5-bit multiplier for signal <$mult0003> created at line 207.
  278. Found 32-bit shifter logical right for signal <$n0000> created at line 105.
  279. Found 5-bit register for signal <i>.
  280. Found 5-bit subtractor for signal <i$addsub0000> created at line 155.
  281. Found 32-bit register for signal <i_quo>.
  282. Found 32-bit register for signal <i_re>.
  283. Found 32-bit register for signal <k_reg.quo>.
  284. Found 36-bit register for signal <k_reg.re_reg>.
  285. Found 1-bit register for signal <k_reg.re_sign>.
  286. Found 32-bit register for signal <main_reg.quo>.
  287. Found 32-bit addsub for signal <main_reg.quo$mux0000>.
  288. Found 32-bit register for signal <main_reg.quo_reg>.
  289. Found 32-bit comparator greater for signal <main_reg.quo_reg$cmp_gt0000> created at line 132.
  290. Found 32-bit subtractor for signal <main_reg.quo_reg$mux0000>.
  291. Found 1-bit register for signal <main_reg.quo_sign>.
  292. Found 32-bit comparator greater for signal <main_reg.quo_sign$cmp_gt0000> created at line 132.
  293. Found 36-bit register for signal <main_reg.re_reg>.
  294. Found 36-bit comparator greater for signal <main_reg.re_reg$cmp_gt0000> created at line 142.
  295. Found 1-bit xor2 for signal <main_reg.re_reg$cmp_ne0000> created at line 141.
  296. Found 36-bit addsub for signal <main_reg.re_reg$mux0000>.
  297. Found 1-bit register for signal <main_reg.re_sign>.
  298. Found 32-bit addsub for signal <quo$share0000>.
  299. Found 33x32-bit multiplier for signal <quo_tmp$mult0001> created at line 120.
  300. Found 32-bit comparator greatequal for signal <re$cmp_ge0000> created at line 207.
  301. Found 32-bit comparator greatequal for signal <re$cmp_ge0001> created at line 207.
  302. Found 32-bit comparator greatequal for signal <re$cmp_ge0002> created at line 207.
  303. Found 32-bit comparator greatequal for signal <re$cmp_ge0003> created at line 207.
  304. Found 32-bit comparator greatequal for signal <re$cmp_ge0004> created at line 207.
  305. Found 32-bit comparator greatequal for signal <re$cmp_ge0005> created at line 207.
  306. Found 32-bit comparator greatequal for signal <re$cmp_ge0006> created at line 207.
  307. Found 32-bit comparator greatequal for signal <re$cmp_ge0007> created at line 207.
  308. Found 32-bit comparator greatequal for signal <re$cmp_ge0008> created at line 207.
  309. Found 32-bit comparator greatequal for signal <re$cmp_ge0009> created at line 207.
  310. Found 32-bit comparator greatequal for signal <re$cmp_ge0010> created at line 207.
  311. Found 32-bit comparator greatequal for signal <re$cmp_ge0011> created at line 207.
  312. Found 32-bit comparator greatequal for signal <re$cmp_ge0012> created at line 207.
  313. Found 32-bit comparator greatequal for signal <re$cmp_ge0013> created at line 207.
  314. Found 32-bit comparator greatequal for signal <re$cmp_ge0014> created at line 207.
  315. Found 32-bit comparator greatequal for signal <re$cmp_ge0015> created at line 207.
  316. Found 33x4-bit multiplier for signal <re$mult0004> created at line 207.
  317. Found 33x4-bit multiplier for signal <re$mult0005> created at line 207.
  318. Found 33x4-bit multiplier for signal <re$mult0006> created at line 207.
  319. Found 33x3-bit multiplier for signal <re$mult0007> created at line 207.
  320. Found 33x3-bit multiplier for signal <re$mult0008> created at line 207.
  321. Found 33x4-bit multiplier for signal <re$mult0009> created at line 207.
  322. Found 33x4-bit multiplier for signal <re$mult0010> created at line 207.
  323. Found 33x4-bit multiplier for signal <re$mult0011> created at line 207.
  324. Found 32-bit addsub for signal <re$share0000>.
  325. Found 32-bit adder for signal <re$sub0000> created at line 207.
  326. Found 32-bit adder for signal <re$sub0001> created at line 207.
  327. Found 32-bit adder for signal <re$sub0002> created at line 207.
  328. Found 32-bit adder for signal <re$sub0003> created at line 207.
  329. Found 32-bit adder for signal <re$sub0004> created at line 207.
  330. Found 32-bit adder for signal <re$sub0005> created at line 207.
  331. Found 32-bit adder for signal <re$sub0006> created at line 207.
  332. Found 33x32-bit multiplier for signal <re_tmp$mult0001> created at line 126.
  333. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<30:1>> created at line 126.
  334. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<0>> created at line 126.
  335. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_shifted_0$mux0000> created at line 107.
  336. Found 36-bit adder for signal <v_re$addsub0000> created at line 196.
  337. Found 36-bit shifter arithmetic right for signal <v_re$shift0000> created at line 200.
  338. Found 1-bit 32-to-1 multiplexer for signal <v_reg.quo_reg_30$mux0000> created at line 115.
  339. Summary:
  340. inferred 1 Finite State Machine(s).
  341. inferred 240 D-type flip-flop(s).
  342. inferred 14 Adder/Subtractor(s).
  343. inferred 14 Multiplier(s).
  344. inferred 19 Comparator(s).
  345. inferred 33 Multiplexer(s).
  346. inferred 2 Combinational logic shifter(s).
  347. Unit <vedic_div32> synthesized.
  348.  
  349. INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
  350.  
  351. =========================================================================
  352. HDL Synthesis Report
  353.  
  354. Macro Statistics
  355. # Multipliers : 14
  356. 33x3-bit multiplier : 2
  357. 33x32-bit multiplier : 2
  358. 33x4-bit multiplier : 6
  359. 34x4-bit multiplier : 1
  360. 34x5-bit multiplier : 3
  361. # Adders/Subtractors : 14
  362. 32-bit adder : 7
  363. 32-bit addsub : 3
  364. 32-bit subtractor : 1
  365. 36-bit adder : 1
  366. 36-bit addsub : 1
  367. 5-bit subtractor : 1
  368. # Registers : 11
  369. 1-bit register : 3
  370. 32-bit register : 5
  371. 36-bit register : 2
  372. 5-bit register : 1
  373. # Latches : 64
  374. 1-bit latch : 62
  375. 31-bit latch : 1
  376. 5-bit latch : 1
  377. # Comparators : 19
  378. 32-bit comparator greatequal : 16
  379. 32-bit comparator greater : 2
  380. 36-bit comparator greater : 1
  381. # Multiplexers : 33
  382. 1-bit 31-to-1 multiplexer : 1
  383. 1-bit 32-to-1 multiplexer : 32
  384. # Logic shifters : 2
  385. 32-bit shifter logical right : 1
  386. 36-bit shifter arithmetic right : 1
  387. # Xors : 1
  388. 1-bit xor2 : 1
  389.  
  390. =========================================================================
  391.  
  392. =========================================================================
  393. * Advanced HDL Synthesis *
  394. =========================================================================
  395.  
  396. Analyzing FSM <FSM_0> for best encoding.
  397. Optimizing FSM <state/FSM> on signal <state[1:4]> with one-hot encoding.
  398. ------------------------
  399. State | Encoding
  400. ------------------------
  401. init_state | 0001
  402. main_state | 0100
  403. wait_state | 1000
  404. fin_state | 0010
  405. ------------------------
  406.  
  407. Synthesizing (advanced) Unit <vedic_div32>.
  408. The following registers are absorbed into accumulator <main_reg.quo>: 1 register on signal <main_reg.quo>.
  409. Unit <vedic_div32> synthesized (advanced).
  410.  
  411. =========================================================================
  412. Advanced HDL Synthesis Report
  413.  
  414. Macro Statistics
  415. # FSMs : 1
  416. # Multipliers : 14
  417. 33x3-bit multiplier : 2
  418. 33x32-bit multiplier : 2
  419. 33x4-bit multiplier : 6
  420. 34x4-bit multiplier : 1
  421. 34x5-bit multiplier : 3
  422. # Adders/Subtractors : 13
  423. 32-bit adder : 7
  424. 32-bit addsub : 2
  425. 32-bit subtractor : 1
  426. 36-bit adder : 1
  427. 36-bit addsub : 1
  428. 5-bit subtractor : 1
  429. # Accumulators : 1
  430. 32-bit updown loadable accumulator : 1
  431. # Registers : 208
  432. Flip-Flops : 208
  433. # Latches : 64
  434. 1-bit latch : 62
  435. 31-bit latch : 1
  436. 5-bit latch : 1
  437. # Comparators : 19
  438. 32-bit comparator greatequal : 16
  439. 32-bit comparator greater : 2
  440. 36-bit comparator greater : 1
  441. # Multiplexers : 33
  442. 1-bit 31-to-1 multiplexer : 1
  443. 1-bit 32-to-1 multiplexer : 32
  444. # Logic shifters : 2
  445. 32-bit shifter logical right : 1
  446. 36-bit shifter arithmetic right : 1
  447. # Xors : 1
  448. 1-bit xor2 : 1
  449.  
  450. =========================================================================
  451.  
  452. =========================================================================
  453. * Low Level Synthesis *
  454. =========================================================================
  455. WARNING:Xst:2677 - Node <Mmult_quo_tmp_mult00013> of sequential type is unconnected in block <vedic_div32>.
  456. WARNING:Xst:2677 - Node <Mmult_re_tmp_mult00013> of sequential type is unconnected in block <vedic_div32>.
  457.  
  458. Optimizing unit <vedic_div32> ...
  459.  
  460. Mapping all equations...
  461. Building and optimizing final netlist ...
  462. Found area constraint ratio of 100 (+ 5) on block vedic_div32, actual ratio is 18.
  463.  
  464. Final Macro Processing ...
  465.  
  466. =========================================================================
  467. Final Register Report
  468.  
  469. Macro Statistics
  470. # Registers : 243
  471. Flip-Flops : 243
  472.  
  473. =========================================================================
  474.  
  475. =========================================================================
  476. * Partition Report *
  477. =========================================================================
  478.  
  479. Partition Implementation Status
  480. -------------------------------
  481.  
  482. No Partitions were found in this design.
  483.  
  484. -------------------------------
  485.  
  486. =========================================================================
  487. * Final Report *
  488. =========================================================================
  489. Final Results
  490. RTL Top Level Output File Name : vedic_div32.ngr
  491. Top Level Output File Name : vedic_div32
  492. Output Format : NGC
  493. Optimization Goal : Speed
  494. Keep Hierarchy : No
  495.  
  496. Design Statistics
  497. # IOs : 130
  498.  
  499. Cell Usage :
  500. # BELS : 5831
  501. # GND : 1
  502. # INV : 217
  503. # LUT1 : 4
  504. # LUT2 : 614
  505. # LUT3 : 291
  506. # LUT4 : 787
  507. # LUT5 : 363
  508. # LUT6 : 1457
  509. # MUXCY : 1118
  510. # MUXF7 : 102
  511. # VCC : 1
  512. # XORCY : 876
  513. # FlipFlops/Latches : 341
  514. # FD : 156
  515. # FDE : 70
  516. # FDR : 2
  517. # FDS : 15
  518. # LDC : 1
  519. # LDCP : 97
  520. # Clock Buffers : 2
  521. # BUFG : 1
  522. # BUFGP : 1
  523. # IO Buffers : 129
  524. # IBUF : 65
  525. # OBUF : 64
  526. # DSPs : 6
  527. # DSP48E : 6
  528. =========================================================================
  529.  
  530. Device utilization summary:
  531. ---------------------------
  532.  
  533. Selected Device : 5vlx50tff1136-1
  534.  
  535.  
  536. Slice Logic Utilization:
  537. Number of Slice Registers: 341 out of 28800 1%
  538. Number of Slice LUTs: 3733 out of 28800 12%
  539. Number used as Logic: 3733 out of 28800 12%
  540.  
  541. Slice Logic Distribution:
  542. Number of LUT Flip Flop pairs used: 3780
  543. Number with an unused Flip Flop: 3439 out of 3780 90%
  544. Number with an unused LUT: 47 out of 3780 1%
  545. Number of fully used LUT-FF pairs: 294 out of 3780 7%
  546. Number of unique control sets: 104
  547.  
  548. IO Utilization:
  549. Number of IOs: 130
  550. Number of bonded IOBs: 130 out of 480 27%
  551.  
  552. Specific Feature Utilization:
  553. Number of BUFG/BUFGCTRLs: 2 out of 32 6%
  554. Number of DSP48Es: 6 out of 48 12%
  555.  
  556. ---------------------------
  557. Partition Resource Summary:
  558. ---------------------------
  559.  
  560. No Partitions were found in this design.
  561.  
  562. ---------------------------
  563.  
  564.  
  565. =========================================================================
  566. TIMING REPORT
  567.  
  568. NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
  569. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
  570. GENERATED AFTER PLACE-and-ROUTE.
  571.  
  572. Clock Information:
  573. ------------------
  574. -----------------------------------+------------------------+-------+
  575. Clock Signal | Clock buffer(FF name) | Load |
  576. -----------------------------------+------------------------+-------+
  577. mclk1 | BUFGP | 243 |
  578. divisor<0> | IBUF+BUFG | 98 |
  579. -----------------------------------+------------------------+-------+
  580.  
  581. Asynchronous Control Signals Information:
  582. ----------------------------------------
  583. -------------------------------------------------------------+--------------------------+-------+
  584. Control Signal | Buffer(FF name) | Load |
  585. -------------------------------------------------------------+--------------------------+-------+
  586. b_n_0__and0000(b_n_0__and00001:O) | NONE(b_n_0) | 1 |
  587. b_n_0__and0001(b_n_0__and00011:O) | NONE(b_n_0) | 1 |
  588. b_n_10__and0000(b_n_10__and00001:O) | NONE(b_n_10) | 1 |
  589. b_n_10__and0001(b_n_10__and00011:O) | NONE(b_n_10) | 1 |
  590. b_n_11__and0000(b_n_11__and00001:O) | NONE(b_n_11) | 1 |
  591. b_n_11__and0001(b_n_11__and00011:O) | NONE(b_n_11) | 1 |
  592. b_n_12__and0000(b_n_12__and00001:O) | NONE(b_n_12) | 1 |
  593. b_n_12__and0001(b_n_12__and00011:O) | NONE(b_n_12) | 1 |
  594. b_n_13__and0000(b_n_13__and00001:O) | NONE(b_n_13) | 1 |
  595. b_n_13__and0001(b_n_13__and00011:O) | NONE(b_n_13) | 1 |
  596. b_n_14__and0000(b_n_14__and00001:O) | NONE(b_n_14) | 1 |
  597. b_n_14__and0001(b_n_14__and00011:O) | NONE(b_n_14) | 1 |
  598. b_n_15__and0000(b_n_15__and00001:O) | NONE(b_n_15) | 1 |
  599. b_n_15__and0001(b_n_15__and00011:O) | NONE(b_n_15) | 1 |
  600. b_n_16__and0000(b_n_16__and00001:O) | NONE(b_n_16) | 1 |
  601. b_n_16__and0001(b_n_16__and00011:O) | NONE(b_n_16) | 1 |
  602. b_n_17__and0000(b_n_17__and00001:O) | NONE(b_n_17) | 1 |
  603. b_n_17__and0001(b_n_17__and00011:O) | NONE(b_n_17) | 1 |
  604. b_n_18__and0000(b_n_18__and00001:O) | NONE(b_n_18) | 1 |
  605. b_n_18__and0001(b_n_18__and00011:O) | NONE(b_n_18) | 1 |
  606. b_n_19__and0000(b_n_19__and00001:O) | NONE(b_n_19) | 1 |
  607. b_n_19__and0001(b_n_19__and00011:O) | NONE(b_n_19) | 1 |
  608. b_n_1__and0000(b_n_1__and00001:O) | NONE(b_n_1) | 1 |
  609. b_n_1__and0001(b_n_1__and00011:O) | NONE(b_n_1) | 1 |
  610. b_n_20__and0000(b_n_20__and00001:O) | NONE(b_n_20) | 1 |
  611. b_n_20__and0001(b_n_20__and00011:O) | NONE(b_n_20) | 1 |
  612. b_n_21__and0000(b_n_21__and00001:O) | NONE(b_n_21) | 1 |
  613. b_n_21__and0001(b_n_21__and00011:O) | NONE(b_n_21) | 1 |
  614. b_n_22__and0000(b_n_22__and00001:O) | NONE(b_n_22) | 1 |
  615. b_n_22__and0001(b_n_22__and00011:O) | NONE(b_n_22) | 1 |
  616. b_n_23__and0000(b_n_23__and00001:O) | NONE(b_n_23) | 1 |
  617. b_n_23__and0001(b_n_23__and00011:O) | NONE(b_n_23) | 1 |
  618. b_n_24__and0000(b_n_24__and00001:O) | NONE(b_n_24) | 1 |
  619. b_n_24__and0001(b_n_24__and00011:O) | NONE(b_n_24) | 1 |
  620. b_n_25__and0000(b_n_25__and00001:O) | NONE(b_n_25) | 1 |
  621. b_n_25__and0001(b_n_25__and00011:O) | NONE(b_n_25) | 1 |
  622. b_n_26__and0000(b_n_26__and00001:O) | NONE(b_n_26) | 1 |
  623. b_n_26__and0001(b_n_26__and00011:O) | NONE(b_n_26) | 1 |
  624. b_n_27__and0000(b_n_27__and00001:O) | NONE(b_n_27) | 1 |
  625. b_n_27__and0001(b_n_27__and00011:O) | NONE(b_n_27) | 1 |
  626. b_n_28__and0000(b_n_28__and00001:O) | NONE(b_n_28) | 1 |
  627. b_n_28__and0001(b_n_28__and00011:O) | NONE(b_n_28) | 1 |
  628. b_n_29__and0000(b_n_29__and00001:O) | NONE(b_n_29) | 1 |
  629. b_n_29__and0001(b_n_29__and00011:O) | NONE(b_n_29) | 1 |
  630. b_n_2__and0000(b_n_2__and00001:O) | NONE(b_n_2) | 1 |
  631. b_n_2__and0001(b_n_2__and00011:O) | NONE(b_n_2) | 1 |
  632. b_n_30__and0000(b_n_30__and00001:O) | NONE(b_n_30) | 1 |
  633. b_n_30__and0001(b_n_30__and00011:O) | NONE(b_n_30) | 1 |
  634. b_n_3__and0000(b_n_3__and00001:O) | NONE(b_n_3) | 1 |
  635. b_n_3__and0001(b_n_3__and00011:O) | NONE(b_n_3) | 1 |
  636. b_n_4__and0000(b_n_4__and00001:O) | NONE(b_n_4) | 1 |
  637. b_n_4__and0001(b_n_4__and00011:O) | NONE(b_n_4) | 1 |
  638. b_n_5__and0000(b_n_5__and00001:O) | NONE(b_n_5) | 1 |
  639. b_n_5__and0001(b_n_5__and00011:O) | NONE(b_n_5) | 1 |
  640. b_n_6__and0000(b_n_6__and00001:O) | NONE(b_n_6) | 1 |
  641. b_n_6__and0001(b_n_6__and00011:O) | NONE(b_n_6) | 1 |
  642. b_n_7__and0000(b_n_7__and00001:O) | NONE(b_n_7) | 1 |
  643. b_n_7__and0001(b_n_7__and00011:O) | NONE(b_n_7) | 1 |
  644. b_n_8__and0000(b_n_8__and00001:O) | NONE(b_n_8) | 1 |
  645. b_n_8__and0001(b_n_8__and00011:O) | NONE(b_n_8) | 1 |
  646. b_n_9__and0000(b_n_9__and00001:O) | NONE(b_n_9) | 1 |
  647. b_n_9__and0001(b_n_9__and00011:O) | NONE(b_n_9) | 1 |
  648. b_n_or0000(b_n_or0000177:O) | NONE(init_reg.quo_reg_31)| 1 |
  649. init_reg.quo_reg_0__and0000(init_reg.quo_reg_0__and00001:O) | NONE(init_reg.quo_reg_0) | 1 |
  650. init_reg.quo_reg_0__and0001(init_reg.quo_reg_0__and00011:O) | NONE(init_reg.quo_reg_0) | 1 |
  651. init_reg.quo_reg_10__and0000(init_reg.quo_reg_10__and00001:O)| NONE(init_reg.quo_reg_10)| 1 |
  652. init_reg.quo_reg_10__or0000(init_reg.quo_reg_10__or00001:O) | NONE(init_reg.quo_reg_10)| 1 |
  653. init_reg.quo_reg_11__and0000(init_reg.quo_reg_11__and00001:O)| NONE(init_reg.quo_reg_11)| 1 |
  654. init_reg.quo_reg_11__or0000(init_reg.quo_reg_11__or00001:O) | NONE(init_reg.quo_reg_11)| 1 |
  655. init_reg.quo_reg_12__and0000(init_reg.quo_reg_12__and00001:O)| NONE(init_reg.quo_reg_12)| 1 |
  656. init_reg.quo_reg_12__or0000(init_reg.quo_reg_12__or00001:O) | NONE(init_reg.quo_reg_12)| 1 |
  657. init_reg.quo_reg_13__and0000(init_reg.quo_reg_13__and00001:O)| NONE(init_reg.quo_reg_13)| 1 |
  658. init_reg.quo_reg_13__or0000(init_reg.quo_reg_13__or00001:O) | NONE(init_reg.quo_reg_13)| 1 |
  659. init_reg.quo_reg_14__and0000(init_reg.quo_reg_14__and00001:O)| NONE(init_reg.quo_reg_14)| 1 |
  660. init_reg.quo_reg_14__or0000(init_reg.quo_reg_14__or00001:O) | NONE(init_reg.quo_reg_14)| 1 |
  661. init_reg.quo_reg_15__and0000(init_reg.quo_reg_15__and00001:O)| NONE(init_reg.quo_reg_15)| 1 |
  662. init_reg.quo_reg_15__or0000(init_reg.quo_reg_15__or00001:O) | NONE(init_reg.quo_reg_15)| 1 |
  663. init_reg.quo_reg_16__and0000(init_reg.quo_reg_16__and00001:O)| NONE(init_reg.quo_reg_16)| 1 |
  664. init_reg.quo_reg_16__or0000(init_reg.quo_reg_16__or00001:O) | NONE(init_reg.quo_reg_16)| 1 |
  665. init_reg.quo_reg_17__and0000(init_reg.quo_reg_17__and00001:O)| NONE(init_reg.quo_reg_17)| 1 |
  666. init_reg.quo_reg_17__or0000(init_reg.quo_reg_17__or00001:O) | NONE(init_reg.quo_reg_17)| 1 |
  667. init_reg.quo_reg_18__and0000(init_reg.quo_reg_18__and00001:O)| NONE(init_reg.quo_reg_18)| 1 |
  668. init_reg.quo_reg_18__or0000(init_reg.quo_reg_18__or00001:O) | NONE(init_reg.quo_reg_18)| 1 |
  669. init_reg.quo_reg_19__and0000(init_reg.quo_reg_19__and00001:O)| NONE(init_reg.quo_reg_19)| 1 |
  670. init_reg.quo_reg_19__or0000(init_reg.quo_reg_19__or00001:O) | NONE(init_reg.quo_reg_19)| 1 |
  671. init_reg.quo_reg_1__and0000(init_reg.quo_reg_1__and00001:O) | NONE(init_reg.quo_reg_1) | 1 |
  672. init_reg.quo_reg_1__or0000(init_reg.quo_reg_1__or00001:O) | NONE(init_reg.quo_reg_1) | 1 |
  673. init_reg.quo_reg_20__and0000(init_reg.quo_reg_20__and00001:O)| NONE(init_reg.quo_reg_20)| 1 |
  674. init_reg.quo_reg_20__or0000(init_reg.quo_reg_20__or00001:O) | NONE(init_reg.quo_reg_20)| 1 |
  675. init_reg.quo_reg_21__and0000(init_reg.quo_reg_21__and00001:O)| NONE(init_reg.quo_reg_21)| 1 |
  676. init_reg.quo_reg_21__or0000(init_reg.quo_reg_21__or00001:O) | NONE(init_reg.quo_reg_21)| 1 |
  677. init_reg.quo_reg_22__and0000(init_reg.quo_reg_22__and00001:O)| NONE(init_reg.quo_reg_22)| 1 |
  678. init_reg.quo_reg_22__or0000(init_reg.quo_reg_22__or00001:O) | NONE(init_reg.quo_reg_22)| 1 |
  679. init_reg.quo_reg_23__and0000(init_reg.quo_reg_23__and00001:O)| NONE(init_reg.quo_reg_23)| 1 |
  680. init_reg.quo_reg_23__or0000(init_reg.quo_reg_23__or00001:O) | NONE(init_reg.quo_reg_23)| 1 |
  681. init_reg.quo_reg_24__and0000(init_reg.quo_reg_24__and00001:O)| NONE(init_reg.quo_reg_24)| 1 |
  682. init_reg.quo_reg_24__or0000(init_reg.quo_reg_24__or00001:O) | NONE(init_reg.quo_reg_24)| 1 |
  683. init_reg.quo_reg_25__and0000(init_reg.quo_reg_25__and00001:O)| NONE(init_reg.quo_reg_25)| 1 |
  684. init_reg.quo_reg_25__or0000(init_reg.quo_reg_25__or00001:O) | NONE(init_reg.quo_reg_25)| 1 |
  685. init_reg.quo_reg_26__and0000(init_reg.quo_reg_26__and00001:O)| NONE(init_reg.quo_reg_26)| 1 |
  686. init_reg.quo_reg_26__or0000(init_reg.quo_reg_26__or0000:O) | NONE(init_reg.quo_reg_26)| 1 |
  687. init_reg.quo_reg_27__and0000(init_reg.quo_reg_27__and00001:O)| NONE(init_reg.quo_reg_27)| 1 |
  688. init_reg.quo_reg_27__or0000(init_reg.quo_reg_27__or00001:O) | NONE(init_reg.quo_reg_27)| 1 |
  689. init_reg.quo_reg_28__and0000(init_reg.quo_reg_28__and00001:O)| NONE(init_reg.quo_reg_28)| 1 |
  690. init_reg.quo_reg_28__or0000(init_reg.quo_reg_28__or00001:O) | NONE(init_reg.quo_reg_28)| 1 |
  691. init_reg.quo_reg_29__and0000(init_reg.quo_reg_29__and00001:O)| NONE(init_reg.quo_reg_29)| 1 |
  692. init_reg.quo_reg_29__or0000(init_reg.quo_reg_29__or00001:O) | NONE(init_reg.quo_reg_29)| 1 |
  693. init_reg.quo_reg_2__and0000(init_reg.quo_reg_2__and00001:O) | NONE(init_reg.quo_reg_2) | 1 |
  694. init_reg.quo_reg_2__or0000(init_reg.quo_reg_2__or00001:O) | NONE(init_reg.quo_reg_2) | 1 |
  695. init_reg.quo_reg_30__and0000(init_reg.quo_reg_30__and00001:O)| NONE(init_reg.quo_reg_30)| 1 |
  696. init_reg.quo_reg_30__or0000(init_reg.quo_reg_30__or00001:O) | NONE(init_reg.quo_reg_30)| 1 |
  697. init_reg.quo_reg_3__and0000(init_reg.quo_reg_3__and00001:O) | NONE(init_reg.quo_reg_3) | 1 |
  698. init_reg.quo_reg_3__or0000(init_reg.quo_reg_3__or00001:O) | NONE(init_reg.quo_reg_3) | 1 |
  699. init_reg.quo_reg_4__and0000(init_reg.quo_reg_4__and00001:O) | NONE(init_reg.quo_reg_4) | 1 |
  700. init_reg.quo_reg_4__or0000(init_reg.quo_reg_4__or00001:O) | NONE(init_reg.quo_reg_4) | 1 |
  701. init_reg.quo_reg_5__and0000(init_reg.quo_reg_5__and00001:O) | NONE(init_reg.quo_reg_5) | 1 |
  702. init_reg.quo_reg_5__or0000(init_reg.quo_reg_5__or00001:O) | NONE(init_reg.quo_reg_5) | 1 |
  703. init_reg.quo_reg_6__and0000(init_reg.quo_reg_6__and00001:O) | NONE(init_reg.quo_reg_6) | 1 |
  704. init_reg.quo_reg_6__or0000(init_reg.quo_reg_6__or00001:O) | NONE(init_reg.quo_reg_6) | 1 |
  705. init_reg.quo_reg_7__and0000(init_reg.quo_reg_7__and00001:O) | NONE(init_reg.quo_reg_7) | 1 |
  706. init_reg.quo_reg_7__or0000(init_reg.quo_reg_7__or00001:O) | NONE(init_reg.quo_reg_7) | 1 |
  707. init_reg.quo_reg_8__and0000(init_reg.quo_reg_8__and00001:O) | NONE(init_reg.quo_reg_8) | 1 |
  708. init_reg.quo_reg_8__or0000(init_reg.quo_reg_8__or00001:O) | NONE(init_reg.quo_reg_8) | 1 |
  709. init_reg.quo_reg_9__and0000(init_reg.quo_reg_9__and00001:O) | NONE(init_reg.quo_reg_9) | 1 |
  710. init_reg.quo_reg_9__or0000(init_reg.quo_reg_9__or00001:O) | NONE(init_reg.quo_reg_9) | 1 |
  711. init_reg.re_reg_10__and0000(init_reg.re_reg_10__and00001:O) | NONE(init_reg.re_reg_10) | 1 |
  712. init_reg.re_reg_10__or0000(init_reg.re_reg_10__or0000:O) | NONE(init_reg.re_reg_10) | 1 |
  713. init_reg.re_reg_11__and0000(init_reg.re_reg_11__and00001:O) | NONE(init_reg.re_reg_11) | 1 |
  714. init_reg.re_reg_11__or0000(init_reg.re_reg_11__or0000:O) | NONE(init_reg.re_reg_11) | 1 |
  715. init_reg.re_reg_12__and0000(init_reg.re_reg_12__and00001:O) | NONE(init_reg.re_reg_12) | 1 |
  716. init_reg.re_reg_12__or0000(init_reg.re_reg_12__or0000:O) | NONE(init_reg.re_reg_12) | 1 |
  717. init_reg.re_reg_13__and0000(init_reg.re_reg_13__and00001:O) | NONE(init_reg.re_reg_13) | 1 |
  718. init_reg.re_reg_13__or0000(init_reg.re_reg_13__or0000_f7:O) | NONE(init_reg.re_reg_13) | 1 |
  719. init_reg.re_reg_14__and0000(init_reg.re_reg_14__and00001:O) | NONE(init_reg.re_reg_14) | 1 |
  720. init_reg.re_reg_14__or0000(init_reg.re_reg_14__or0000:O) | NONE(init_reg.re_reg_14) | 1 |
  721. init_reg.re_reg_15__and0000(init_reg.re_reg_15__and00001:O) | NONE(init_reg.re_reg_15) | 1 |
  722. init_reg.re_reg_15__or0000(init_reg.re_reg_15__or00001:O) | NONE(init_reg.re_reg_15) | 1 |
  723. init_reg.re_reg_16__and0000(init_reg.re_reg_16__and00001:O) | NONE(init_reg.re_reg_16) | 1 |
  724. init_reg.re_reg_16__or0000(init_reg.re_reg_16__or00001:O) | NONE(init_reg.re_reg_16) | 1 |
  725. init_reg.re_reg_17__and0000(init_reg.re_reg_17__and00001:O) | NONE(init_reg.re_reg_17) | 1 |
  726. init_reg.re_reg_17__or0000(init_reg.re_reg_17__or00001:O) | NONE(init_reg.re_reg_17) | 1 |
  727. init_reg.re_reg_18__and0000(init_reg.re_reg_18__and00001:O) | NONE(init_reg.re_reg_18) | 1 |
  728. init_reg.re_reg_18__or0000(init_reg.re_reg_18__or0000:O) | NONE(init_reg.re_reg_18) | 1 |
  729. init_reg.re_reg_19__and0000(init_reg.re_reg_19__and00001:O) | NONE(init_reg.re_reg_19) | 1 |
  730. init_reg.re_reg_19__or0000(init_reg.re_reg_19__or0000:O) | NONE(init_reg.re_reg_19) | 1 |
  731. init_reg.re_reg_1__and0000(init_reg.re_reg_1__and00001:O) | NONE(init_reg.re_reg_1) | 1 |
  732. init_reg.re_reg_1__or0000(init_reg.re_reg_1__or00001:O) | NONE(init_reg.re_reg_1) | 1 |
  733. init_reg.re_reg_20__and0000(init_reg.re_reg_20__and00001:O) | NONE(init_reg.re_reg_20) | 1 |
  734. init_reg.re_reg_20__or0000(init_reg.re_reg_20__or0000:O) | NONE(init_reg.re_reg_20) | 1 |
  735. init_reg.re_reg_21__and0000(init_reg.re_reg_21__and00001:O) | NONE(init_reg.re_reg_21) | 1 |
  736. init_reg.re_reg_21__or0000(init_reg.re_reg_21__or0000:O) | NONE(init_reg.re_reg_21) | 1 |
  737. init_reg.re_reg_22__and0000(init_reg.re_reg_22__and00001:O) | NONE(init_reg.re_reg_22) | 1 |
  738. init_reg.re_reg_22__or0000(init_reg.re_reg_22__or00001:O) | NONE(init_reg.re_reg_22) | 1 |
  739. init_reg.re_reg_23__and0000(init_reg.re_reg_23__and00001:O) | NONE(init_reg.re_reg_23) | 1 |
  740. init_reg.re_reg_23__or0000(init_reg.re_reg_23__or00001:O) | NONE(init_reg.re_reg_23) | 1 |
  741. init_reg.re_reg_24__and0000(init_reg.re_reg_24__and00001:O) | NONE(init_reg.re_reg_24) | 1 |
  742. init_reg.re_reg_24__or0000(init_reg.re_reg_24__or00001:O) | NONE(init_reg.re_reg_24) | 1 |
  743. init_reg.re_reg_25__and0000(init_reg.re_reg_25__and00001:O) | NONE(init_reg.re_reg_25) | 1 |
  744. init_reg.re_reg_25__or0000(init_reg.re_reg_25__or00001:O) | NONE(init_reg.re_reg_25) | 1 |
  745. init_reg.re_reg_26__and0000(init_reg.re_reg_26__and00001:O) | NONE(init_reg.re_reg_26) | 1 |
  746. init_reg.re_reg_26__or0000(init_reg.re_reg_26__or0000:O) | NONE(init_reg.re_reg_26) | 1 |
  747. init_reg.re_reg_27__and0000(init_reg.re_reg_27__and00001:O) | NONE(init_reg.re_reg_27) | 1 |
  748. init_reg.re_reg_27__or0000(init_reg.re_reg_27__or0000:O) | NONE(init_reg.re_reg_27) | 1 |
  749. init_reg.re_reg_28__and0000(init_reg.re_reg_28__and00001:O) | NONE(init_reg.re_reg_28) | 1 |
  750. init_reg.re_reg_28__or0000(init_reg.re_reg_28__or00001:O) | NONE(init_reg.re_reg_28) | 1 |
  751. init_reg.re_reg_29__and0000(init_reg.re_reg_29__and00001:O) | NONE(init_reg.re_reg_29) | 1 |
  752. init_reg.re_reg_29__or0000(init_reg.re_reg_29__or00001_f7:O) | NONE(init_reg.re_reg_29) | 1 |
  753. init_reg.re_reg_2__and0000(init_reg_re_reg_2_mux00311:O) | NONE(init_reg.re_reg_2) | 1 |
  754. init_reg.re_reg_2__or0000(init_reg.re_reg_2__or00001:O) | NONE(init_reg.re_reg_2) | 1 |
  755. init_reg.re_reg_30__and0000(init_reg.re_reg_30__and00001:O) | NONE(init_reg.re_reg_30) | 1 |
  756. init_reg.re_reg_30__or0000(init_reg.re_reg_30__or0000_f7:O) | NONE(init_reg.re_reg_30) | 1 |
  757. init_reg.re_reg_3__and0000(init_reg_re_reg_3_mux00311:O) | NONE(init_reg.re_reg_3) | 1 |
  758. init_reg.re_reg_3__or0000(init_reg.re_reg_3__or00001:O) | NONE(init_reg.re_reg_3) | 1 |
  759. init_reg.re_reg_4__and0000(init_reg.re_reg_4__and00001:O) | NONE(init_reg.re_reg_4) | 1 |
  760. init_reg.re_reg_4__or0000(init_reg.re_reg_4__or00001:O) | NONE(init_reg.re_reg_4) | 1 |
  761. init_reg.re_reg_5__and0000(init_reg_re_reg_5_mux003181_f7:O) | NONE(init_reg.re_reg_5) | 1 |
  762. init_reg.re_reg_5__or0000(init_reg.re_reg_5__or00001:O) | NONE(init_reg.re_reg_5) | 1 |
  763. init_reg.re_reg_6__and0000(init_reg.re_reg_6__and00001:O) | NONE(init_reg.re_reg_6) | 1 |
  764. init_reg.re_reg_6__or0000(init_reg.re_reg_6__or00001:O) | NONE(init_reg.re_reg_6) | 1 |
  765. init_reg.re_reg_7__and0000(init_reg.re_reg_7__and000011:O) | NONE(init_reg.re_reg_7) | 1 |
  766. init_reg.re_reg_7__or0000(init_reg.re_reg_7__or0000:O) | NONE(init_reg.re_reg_7) | 1 |
  767. init_reg.re_reg_8__and0000(init_reg.re_reg_8__and00001:O) | NONE(init_reg.re_reg_8) | 1 |
  768. init_reg.re_reg_8__or0000(init_reg.re_reg_8__or0000:O) | NONE(init_reg.re_reg_8) | 1 |
  769. init_reg.re_reg_9__and0000(init_reg.re_reg_9__and00001:O) | NONE(init_reg.re_reg_9) | 1 |
  770. init_reg.re_reg_9__or0000(init_reg.re_reg_9__or0000:O) | NONE(init_reg.re_reg_9) | 1 |
  771. shift_val_0__or0000(shift_val_0__or00001:O) | NONE(shift_val_0) | 1 |
  772. shift_val_0__or0001(shift_val_0__or00011:O) | NONE(shift_val_0) | 1 |
  773. shift_val_1__and0000(shift_val_1__and00001:O) | NONE(shift_val_1) | 1 |
  774. shift_val_1__or0000(shift_val_1__or00001:O) | NONE(shift_val_1) | 1 |
  775. shift_val_2__and0000(shift_val_2__and00001:O) | NONE(shift_val_2) | 1 |
  776. shift_val_2__or0000(shift_val_2__or00001:O) | NONE(shift_val_2) | 1 |
  777. shift_val_3__and0000(shift_val_3__and00001:O) | NONE(shift_val_3) | 1 |
  778. shift_val_3__or0000(shift_val_3__or00001:O) | NONE(shift_val_3) | 1 |
  779. shift_val_4__and0000(shift_val_4__and00001:O) | NONE(shift_val_4) | 1 |
  780. shift_val_4__or0000(shift_val_4__or00001:O) | NONE(shift_val_4) | 1 |
  781. -------------------------------------------------------------+--------------------------+-------+
  782.  
  783. Timing Summary:
  784. ---------------
  785. Speed Grade: -1
  786.  
  787. Minimum period: 16.230ns (Maximum Frequency: 61.615MHz)
  788. Minimum input arrival time before clock: 11.737ns
  789. Maximum output required time after clock: 12.435ns
  790. Maximum combinational path delay: 16.698ns
  791.  
  792. Timing Detail:
  793. --------------
  794. All values displayed in nanoseconds (ns)
  795.  
  796. =========================================================================
  797. Timing constraint: Default period analysis for Clock 'mclk1'
  798. Clock period: 16.230ns (frequency: 61.615MHz)
  799. Total number of paths / destination ports: 68584870471 / 330
  800. -------------------------------------------------------------------------
  801. Delay: 16.230ns (Levels of Logic = 51)
  802. Source: state_FSM_FFd4 (FF)
  803. Destination: main_reg.quo_reg_31 (FF)
  804. Source Clock: mclk1 rising
  805. Destination Clock: mclk1 rising
  806.  
  807. Data Path: state_FSM_FFd4 to main_reg.quo_reg_31
  808. Gate Net
  809. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  810. ---------------------------------------- ------------
  811. FDR:C->Q 254 0.471 0.648 state_FSM_FFd4 (state_FSM_FFd4)
  812. LUT3:I2->O 6 0.094 0.816 reg_quo_reg<22>1 (reg_quo_reg<22>)
  813. LUT6:I2->O 4 0.094 0.726 Sh1271 (Sh127)
  814. LUT6:I3->O 3 0.094 0.491 Sh1591 (Sh159)
  815. LUT5:I4->O 1 0.094 0.000 Sh175134_G (N7091)
  816. MUXF7:I1->O 2 0.254 0.341 Sh175134 (Sh175)
  817. DSP48E:B3->PCOUT36 1 3.832 0.000 Mmult_quo_tmp_mult0001 (Mmult_quo_tmp_mult0001_PCOUT_to_Mmult_quo_tmp_mult00011_PCIN_36)
  818. DSP48E:PCIN36->PCOUT44 1 2.013 0.000 Mmult_quo_tmp_mult00011 (Mmult_quo_tmp_mult00011_PCOUT_to_Mmult_quo_tmp_mult00012_PCIN_44)
  819. DSP48E:PCIN44->P0 1 1.816 0.480 Mmult_quo_tmp_mult00012 (quo_tmp_mult0001<17>)
  820. LUT6:I5->O 4 0.094 0.805 quo_tmp_mux0001<17>1 (quo_tmp_mux0001<17>)
  821. LUT4:I0->O 0 0.094 0.000 Mcompar_main_reg.quo_reg_cmp_gt0000_lutdi8 (Mcompar_main_reg.quo_reg_cmp_gt0000_lutdi8)
  822. MUXCY:DI->O 1 0.362 0.000 Mcompar_main_reg.quo_reg_cmp_gt0000_cy<8> (Mcompar_main_reg.quo_reg_cmp_gt0000_cy<8>)
  823. MUXCY:CI->O 1 0.026 0.000 Mcompar_main_reg.quo_reg_cmp_gt0000_cy<9> (Mcompar_main_reg.quo_reg_cmp_gt0000_cy<9>)
  824. MUXCY:CI->O 1 0.026 0.000 Mcompar_main_reg.quo_reg_cmp_gt0000_cy<10> (Mcompar_main_reg.quo_reg_cmp_gt0000_cy<10>)
  825. MUXCY:CI->O 1 0.026 0.000 Mcompar_main_reg.quo_reg_cmp_gt0000_cy<11> (Mcompar_main_reg.quo_reg_cmp_gt0000_cy<11>)
  826. MUXCY:CI->O 1 0.026 0.000 Mcompar_main_reg.quo_reg_cmp_gt0000_cy<12> (Mcompar_main_reg.quo_reg_cmp_gt0000_cy<12>)
  827. MUXCY:CI->O 1 0.026 0.000 Mcompar_main_reg.quo_reg_cmp_gt0000_cy<13> (Mcompar_main_reg.quo_reg_cmp_gt0000_cy<13>)
  828. MUXCY:CI->O 1 0.026 0.000 Mcompar_main_reg.quo_reg_cmp_gt0000_cy<14> (Mcompar_main_reg.quo_reg_cmp_gt0000_cy<14>)
  829. MUXCY:CI->O 32 0.254 0.607 Mcompar_main_reg.quo_reg_cmp_gt0000_cy<15> (Mcompar_main_reg.quo_reg_cmp_gt0000_cy<15>)
  830. LUT6:I5->O 0 0.094 0.000 main_reg_quo_reg_mux0001<0>1 (main_reg_quo_reg_mux0001<0>)
  831. MUXCY:DI->O 1 0.362 0.000 Msub_main_reg.quo_reg_mux0000_cy<0> (Msub_main_reg.quo_reg_mux0000_cy<0>)
  832. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<1> (Msub_main_reg.quo_reg_mux0000_cy<1>)
  833. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<2> (Msub_main_reg.quo_reg_mux0000_cy<2>)
  834. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<3> (Msub_main_reg.quo_reg_mux0000_cy<3>)
  835. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<4> (Msub_main_reg.quo_reg_mux0000_cy<4>)
  836. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<5> (Msub_main_reg.quo_reg_mux0000_cy<5>)
  837. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<6> (Msub_main_reg.quo_reg_mux0000_cy<6>)
  838. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<7> (Msub_main_reg.quo_reg_mux0000_cy<7>)
  839. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<8> (Msub_main_reg.quo_reg_mux0000_cy<8>)
  840. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<9> (Msub_main_reg.quo_reg_mux0000_cy<9>)
  841. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<10> (Msub_main_reg.quo_reg_mux0000_cy<10>)
  842. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<11> (Msub_main_reg.quo_reg_mux0000_cy<11>)
  843. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<12> (Msub_main_reg.quo_reg_mux0000_cy<12>)
  844. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<13> (Msub_main_reg.quo_reg_mux0000_cy<13>)
  845. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<14> (Msub_main_reg.quo_reg_mux0000_cy<14>)
  846. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<15> (Msub_main_reg.quo_reg_mux0000_cy<15>)
  847. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<16> (Msub_main_reg.quo_reg_mux0000_cy<16>)
  848. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<17> (Msub_main_reg.quo_reg_mux0000_cy<17>)
  849. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<18> (Msub_main_reg.quo_reg_mux0000_cy<18>)
  850. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<19> (Msub_main_reg.quo_reg_mux0000_cy<19>)
  851. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<20> (Msub_main_reg.quo_reg_mux0000_cy<20>)
  852. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<21> (Msub_main_reg.quo_reg_mux0000_cy<21>)
  853. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<22> (Msub_main_reg.quo_reg_mux0000_cy<22>)
  854. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<23> (Msub_main_reg.quo_reg_mux0000_cy<23>)
  855. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<24> (Msub_main_reg.quo_reg_mux0000_cy<24>)
  856. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<25> (Msub_main_reg.quo_reg_mux0000_cy<25>)
  857. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<26> (Msub_main_reg.quo_reg_mux0000_cy<26>)
  858. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<27> (Msub_main_reg.quo_reg_mux0000_cy<27>)
  859. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<28> (Msub_main_reg.quo_reg_mux0000_cy<28>)
  860. MUXCY:CI->O 1 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<29> (Msub_main_reg.quo_reg_mux0000_cy<29>)
  861. MUXCY:CI->O 0 0.026 0.000 Msub_main_reg.quo_reg_mux0000_cy<30> (Msub_main_reg.quo_reg_mux0000_cy<30>)
  862. XORCY:CI->O 1 0.357 0.000 Msub_main_reg.quo_reg_mux0000_xor<31> (main_reg_quo_reg_mux0000<31>)
  863. FD:D -0.018 main_reg.quo_reg_31
  864. ----------------------------------------
  865. Total 16.230ns (11.315ns logic, 4.915ns route)
  866. (69.7% logic, 30.3% route)
  867.  
  868. =========================================================================
  869. Timing constraint: Default OFFSET IN BEFORE for Clock 'mclk1'
  870. Total number of paths / destination ports: 7 / 7
  871. -------------------------------------------------------------------------
  872. Offset: 2.334ns (Levels of Logic = 2)
  873. Source: go (PAD)
  874. Destination: i_0 (FF)
  875. Destination Clock: mclk1 rising
  876.  
  877. Data Path: go to i_0
  878. Gate Net
  879. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  880. ---------------------------------------- ------------
  881. IBUF:I->O 3 0.818 0.491 go_IBUF (go_IBUF)
  882. LUT3:I2->O 5 0.094 0.358 i_or00011 (i_or0001)
  883. FDS:S 0.573 i_0
  884. ----------------------------------------
  885. Total 2.334ns (1.485ns logic, 0.849ns route)
  886. (63.6% logic, 36.4% route)
  887.  
  888. =========================================================================
  889. Timing constraint: Default OFFSET IN BEFORE for Clock 'divisor<0>'
  890. Total number of paths / destination ports: 9777 / 98
  891. -------------------------------------------------------------------------
  892. Offset: 11.737ns (Levels of Logic = 16)
  893. Source: divisor<6> (PAD)
  894. Destination: b_n_29 (LATCH)
  895. Destination Clock: divisor<0> falling
  896.  
  897. Data Path: divisor<6> to b_n_29
  898. Gate Net
  899. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  900. ---------------------------------------- ------------
  901. IBUF:I->O 128 0.818 1.214 divisor_6_IBUF (divisor_6_IBUF)
  902. LUT6:I0->O 1 0.094 0.000 b_n_mux0031<29>1201 (b_n_mux0031<29>1201)
  903. MUXF7:I1->O 1 0.254 0.576 b_n_mux0031<29>120_f7 (b_n_mux0031<29>120)
  904. LUT6:I4->O 1 0.094 0.336 b_n_mux0031<29>178_SW0 (N232)
  905. MUXF7:S->O 1 0.329 0.480 b_n_mux0031<29>255_SW1_f7 (N696)
  906. LUT6:I5->O 1 0.094 0.576 b_n_mux0031<29>255 (b_n_mux0031<29>255)
  907. LUT6:I4->O 1 0.094 0.973 b_n_mux0031<29>330_SW0 (N5661)
  908. LUT6:I1->O 1 0.094 0.789 b_n_mux0031<29>330 (b_n_mux0031<29>330)
  909. LUT6:I2->O 1 0.094 0.576 b_n_mux0031<29>407_SW0 (N446)
  910. LUT5:I3->O 1 0.094 0.480 b_n_mux0031<29>482_SW0 (N5681)
  911. LUT6:I5->O 2 0.094 0.715 b_n_mux0031<29>482 (b_n_mux0031<29>482)
  912. LUT6:I3->O 1 0.094 0.000 b_n_mux0031<29>562_F (N742)
  913. MUXF7:I0->O 1 0.251 0.480 b_n_mux0031<29>562 (b_n_mux0031<29>562)
  914. LUT5:I4->O 1 0.094 0.789 b_n_mux0031<29>641_SW0 (N294)
  915. LUT6:I2->O 1 0.094 0.973 b_n_mux0031<29>641 (b_n_mux0031<29>641)
  916. LUT6:I1->O 3 0.094 0.000 b_n_mux0031<29>667 (b_n_mux0031<29>)
  917. LDCP:D -0.071 b_n_29
  918. ----------------------------------------
  919. Total 11.737ns (2.780ns logic, 8.957ns route)
  920. (23.7% logic, 76.3% route)
  921.  
  922. =========================================================================
  923. Timing constraint: Default OFFSET OUT AFTER for Clock 'mclk1'
  924. Total number of paths / destination ports: 2656670 / 64
  925. -------------------------------------------------------------------------
  926. Offset: 12.435ns (Levels of Logic = 55)
  927. Source: i_re_1 (FF)
  928. Destination: re<30> (PAD)
  929. Source Clock: mclk1 rising
  930.  
  931. Data Path: i_re_1 to re<30>
  932. Gate Net
  933. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  934. ---------------------------------------- ------------
  935. FD:C->Q 26 0.471 0.915 i_re_1 (i_re_1)
  936. LUT4:I0->O 0 0.094 0.000 Mcompar_re_cmp_ge0013_lutdi (Mcompar_re_cmp_ge0013_lutdi)
  937. MUXCY:DI->O 1 0.362 0.000 Mcompar_re_cmp_ge0013_cy<0> (Mcompar_re_cmp_ge0013_cy<0>)
  938. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<1> (Mcompar_re_cmp_ge0013_cy<1>)
  939. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<2> (Mcompar_re_cmp_ge0013_cy<2>)
  940. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<3> (Mcompar_re_cmp_ge0013_cy<3>)
  941. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<4> (Mcompar_re_cmp_ge0013_cy<4>)
  942. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<5> (Mcompar_re_cmp_ge0013_cy<5>)
  943. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<6> (Mcompar_re_cmp_ge0013_cy<6>)
  944. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<7> (Mcompar_re_cmp_ge0013_cy<7>)
  945. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<8> (Mcompar_re_cmp_ge0013_cy<8>)
  946. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<9> (Mcompar_re_cmp_ge0013_cy<9>)
  947. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<10> (Mcompar_re_cmp_ge0013_cy<10>)
  948. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<11> (Mcompar_re_cmp_ge0013_cy<11>)
  949. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<12> (Mcompar_re_cmp_ge0013_cy<12>)
  950. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<13> (Mcompar_re_cmp_ge0013_cy<13>)
  951. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0013_cy<14> (Mcompar_re_cmp_ge0013_cy<14>)
  952. MUXCY:CI->O 39 0.254 1.102 Mcompar_re_cmp_ge0013_cy<15> (re_cmp_ge0013)
  953. LUT5:I0->O 1 0.094 0.789 re_mux0000<1>211 (N544)
  954. LUT6:I2->O 1 0.094 0.480 re_mux0000<1>102_SW0 (N290)
  955. LUT6:I5->O 1 0.094 0.576 re_mux0000<1>102 (re_mux0000<1>102)
  956. LUT6:I4->O 1 0.094 0.576 re_mux0000<1>171_SW0 (N292)
  957. LUT5:I3->O 1 0.094 0.576 re_mux0000<1>171 (re_mux0000<1>)
  958. LUT3:I1->O 1 0.094 0.000 Maddsub_re_share0000_lut<1> (Maddsub_re_share0000_lut<1>)
  959. MUXCY:S->O 1 0.372 0.000 Maddsub_re_share0000_cy<1> (Maddsub_re_share0000_cy<1>)
  960. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<2> (Maddsub_re_share0000_cy<2>)
  961. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<3> (Maddsub_re_share0000_cy<3>)
  962. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<4> (Maddsub_re_share0000_cy<4>)
  963. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<5> (Maddsub_re_share0000_cy<5>)
  964. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<6> (Maddsub_re_share0000_cy<6>)
  965. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<7> (Maddsub_re_share0000_cy<7>)
  966. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<8> (Maddsub_re_share0000_cy<8>)
  967. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<9> (Maddsub_re_share0000_cy<9>)
  968. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<10> (Maddsub_re_share0000_cy<10>)
  969. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<11> (Maddsub_re_share0000_cy<11>)
  970. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<12> (Maddsub_re_share0000_cy<12>)
  971. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<13> (Maddsub_re_share0000_cy<13>)
  972. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<14> (Maddsub_re_share0000_cy<14>)
  973. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<15> (Maddsub_re_share0000_cy<15>)
  974. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<16> (Maddsub_re_share0000_cy<16>)
  975. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<17> (Maddsub_re_share0000_cy<17>)
  976. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<18> (Maddsub_re_share0000_cy<18>)
  977. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<19> (Maddsub_re_share0000_cy<19>)
  978. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<20> (Maddsub_re_share0000_cy<20>)
  979. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<21> (Maddsub_re_share0000_cy<21>)
  980. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<22> (Maddsub_re_share0000_cy<22>)
  981. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<23> (Maddsub_re_share0000_cy<23>)
  982. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<24> (Maddsub_re_share0000_cy<24>)
  983. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<25> (Maddsub_re_share0000_cy<25>)
  984. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<26> (Maddsub_re_share0000_cy<26>)
  985. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<27> (Maddsub_re_share0000_cy<27>)
  986. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<28> (Maddsub_re_share0000_cy<28>)
  987. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<29> (Maddsub_re_share0000_cy<29>)
  988. XORCY:CI->O 1 0.357 0.973 Maddsub_re_share0000_xor<30> (re_share0000<30>)
  989. LUT5:I0->O 1 0.094 0.336 re<30>1 (re_30_OBUF)
  990. OBUF:I->O 2.452 re_30_OBUF (re<30>)
  991. ----------------------------------------
  992. Total 12.435ns (6.112ns logic, 6.323ns route)
  993. (49.2% logic, 50.8% route)
  994.  
  995. =========================================================================
  996. Timing constraint: Default path analysis
  997. Total number of paths / destination ports: 895370539 / 64
  998. -------------------------------------------------------------------------
  999. Delay: 16.698ns (Levels of Logic = 76)
  1000. Source: divisor<2> (PAD)
  1001. Destination: re<30> (PAD)
  1002.  
  1003. Data Path: divisor<2> to re<30>
  1004. Gate Net
  1005. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  1006. ---------------------------------------- ------------
  1007. IBUF:I->O 126 0.818 0.721 divisor_2_IBUF (divisor_2_IBUF)
  1008. LUT2:I0->O 1 0.094 0.000 Mmult_re_mult0011_Madd_lut<2> (Mmult_re_mult0011_Madd_lut<2>)
  1009. MUXCY:S->O 1 0.372 0.000 Mmult_re_mult0011_Madd_cy<2> (Mmult_re_mult0011_Madd_cy<2>)
  1010. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<3> (Mmult_re_mult0011_Madd_cy<3>)
  1011. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<4> (Mmult_re_mult0011_Madd_cy<4>)
  1012. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<5> (Mmult_re_mult0011_Madd_cy<5>)
  1013. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<6> (Mmult_re_mult0011_Madd_cy<6>)
  1014. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<7> (Mmult_re_mult0011_Madd_cy<7>)
  1015. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<8> (Mmult_re_mult0011_Madd_cy<8>)
  1016. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<9> (Mmult_re_mult0011_Madd_cy<9>)
  1017. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<10> (Mmult_re_mult0011_Madd_cy<10>)
  1018. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<11> (Mmult_re_mult0011_Madd_cy<11>)
  1019. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<12> (Mmult_re_mult0011_Madd_cy<12>)
  1020. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<13> (Mmult_re_mult0011_Madd_cy<13>)
  1021. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<14> (Mmult_re_mult0011_Madd_cy<14>)
  1022. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<15> (Mmult_re_mult0011_Madd_cy<15>)
  1023. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<16> (Mmult_re_mult0011_Madd_cy<16>)
  1024. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<17> (Mmult_re_mult0011_Madd_cy<17>)
  1025. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<18> (Mmult_re_mult0011_Madd_cy<18>)
  1026. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<19> (Mmult_re_mult0011_Madd_cy<19>)
  1027. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<20> (Mmult_re_mult0011_Madd_cy<20>)
  1028. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<21> (Mmult_re_mult0011_Madd_cy<21>)
  1029. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<22> (Mmult_re_mult0011_Madd_cy<22>)
  1030. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<23> (Mmult_re_mult0011_Madd_cy<23>)
  1031. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<24> (Mmult_re_mult0011_Madd_cy<24>)
  1032. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<25> (Mmult_re_mult0011_Madd_cy<25>)
  1033. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<26> (Mmult_re_mult0011_Madd_cy<26>)
  1034. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<27> (Mmult_re_mult0011_Madd_cy<27>)
  1035. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0011_Madd_cy<28> (Mmult_re_mult0011_Madd_cy<28>)
  1036. XORCY:CI->O 1 0.357 0.576 Mmult_re_mult0011_Madd_xor<29> (Mmult_re_mult0011_Madd_29)
  1037. LUT2:I0->O 1 0.094 0.000 Mmult_re_mult0011_Madd1_lut<29> (Mmult_re_mult0011_Madd1_lut<29>)
  1038. MUXCY:S->O 1 0.372 0.000 Mmult_re_mult0011_Madd1_cy<29> (Mmult_re_mult0011_Madd1_cy<29>)
  1039. XORCY:CI->O 1 0.357 0.336 Mmult_re_mult0011_Madd1_xor<30> (re_mult0011<30>)
  1040. INV:I->O 1 0.238 0.000 Madd_re_not0004<30>1_INV_0 (Madd_re_not0004<30>)
  1041. MUXCY:S->O 0 0.372 0.000 Madd_re_sub0006_cy<30> (Madd_re_sub0006_cy<30>)
  1042. XORCY:CI->O 2 0.357 0.794 Madd_re_sub0006_xor<31> (re_sub0006<31>)
  1043. LUT4:I0->O 0 0.094 0.000 Mcompar_re_cmp_ge0015_lutdi15 (Mcompar_re_cmp_ge0015_lutdi15)
  1044. MUXCY:DI->O 32 0.590 0.607 Mcompar_re_cmp_ge0015_cy<15> (re_cmp_ge0015)
  1045. LUT5:I4->O 1 0.094 0.789 re_mux0000<1>211 (N544)
  1046. LUT6:I2->O 1 0.094 0.480 re_mux0000<1>102_SW0 (N290)
  1047. LUT6:I5->O 1 0.094 0.576 re_mux0000<1>102 (re_mux0000<1>102)
  1048. LUT6:I4->O 1 0.094 0.576 re_mux0000<1>171_SW0 (N292)
  1049. LUT5:I3->O 1 0.094 0.576 re_mux0000<1>171 (re_mux0000<1>)
  1050. LUT3:I1->O 1 0.094 0.000 Maddsub_re_share0000_lut<1> (Maddsub_re_share0000_lut<1>)
  1051. MUXCY:S->O 1 0.372 0.000 Maddsub_re_share0000_cy<1> (Maddsub_re_share0000_cy<1>)
  1052. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<2> (Maddsub_re_share0000_cy<2>)
  1053. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<3> (Maddsub_re_share0000_cy<3>)
  1054. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<4> (Maddsub_re_share0000_cy<4>)
  1055. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<5> (Maddsub_re_share0000_cy<5>)
  1056. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<6> (Maddsub_re_share0000_cy<6>)
  1057. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<7> (Maddsub_re_share0000_cy<7>)
  1058. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<8> (Maddsub_re_share0000_cy<8>)
  1059. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<9> (Maddsub_re_share0000_cy<9>)
  1060. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<10> (Maddsub_re_share0000_cy<10>)
  1061. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<11> (Maddsub_re_share0000_cy<11>)
  1062. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<12> (Maddsub_re_share0000_cy<12>)
  1063. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<13> (Maddsub_re_share0000_cy<13>)
  1064. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<14> (Maddsub_re_share0000_cy<14>)
  1065. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<15> (Maddsub_re_share0000_cy<15>)
  1066. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<16> (Maddsub_re_share0000_cy<16>)
  1067. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<17> (Maddsub_re_share0000_cy<17>)
  1068. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<18> (Maddsub_re_share0000_cy<18>)
  1069. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<19> (Maddsub_re_share0000_cy<19>)
  1070. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<20> (Maddsub_re_share0000_cy<20>)
  1071. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<21> (Maddsub_re_share0000_cy<21>)
  1072. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<22> (Maddsub_re_share0000_cy<22>)
  1073. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<23> (Maddsub_re_share0000_cy<23>)
  1074. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<24> (Maddsub_re_share0000_cy<24>)
  1075. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<25> (Maddsub_re_share0000_cy<25>)
  1076. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<26> (Maddsub_re_share0000_cy<26>)
  1077. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<27> (Maddsub_re_share0000_cy<27>)
  1078. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<28> (Maddsub_re_share0000_cy<28>)
  1079. MUXCY:CI->O 1 0.026 0.000 Maddsub_re_share0000_cy<29> (Maddsub_re_share0000_cy<29>)
  1080. XORCY:CI->O 1 0.357 0.973 Maddsub_re_share0000_xor<30> (re_share0000<30>)
  1081. LUT5:I0->O 1 0.094 0.336 re<30>1 (re_30_OBUF)
  1082. OBUF:I->O 2.452 re_30_OBUF (re<30>)
  1083. ----------------------------------------
  1084. Total 16.698ns (9.358ns logic, 7.340ns route)
  1085. (56.0% logic, 44.0% route)
  1086.  
  1087. =========================================================================
  1088.  
  1089.  
  1090. Total REAL time to Xst completion: 1497.00 secs
  1091. Total CPU time to Xst completion: 1496.35 secs
  1092.  
  1093. -->
  1094.  
  1095.  
  1096. Total memory usage is 811236 kilobytes
  1097.  
  1098. Number of errors : 0 ( 0 filtered)
  1099. Number of warnings : 87 ( 0 filtered)
  1100. Number of infos : 38 ( 0 filtered)
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