PSC - Unsigned

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity lights is
    port(
        clk: in std_logic;
        reset: in std_logic;
        red: out std_logic;
        orange: out std_logic;
        green: out std_logic;
        Cathodes: out std_logic_vector(6 downto 0);
        AN0: out std_logic_vector(3 downto 0)
    );
end entity lights;

architecture Behaviour of lights is
    type state_type is (RED_STATE, ORANGE_STATE, GREEN_STATE);
    signal state: state_type := RED_STATE;

    -- Zwiększamy na 33 bity dla pewności
    signal timer: unsigned(32 downto 0) := to_unsigned(4200000000, 33);
    signal diff: unsigned(32 downto 0) := to_unsigned(4200000000, 33);

    signal time_10: integer range 0 to 9 := 0;
    signal time_1: integer range 0 to 9 := 0;
    signal Seven_Segment_10: std_logic_vector(6 downto 0);
    signal Seven_Segment_1: std_logic_vector(6 downto 0);
    signal DivAnods: integer range 0 to 1000000;
    signal clkAN: std_logic := '0';

    -- Typ tablicy zmieniony na unsigned z 33 bitami
    type t_vector is array (0 to 2) of unsigned(32 downto 0);
    signal times_vector: t_vector := (to_unsigned(4000000000, 33),
                                      to_unsigned(300000000, 33),
                                      to_unsigned(4100000000, 33));
    signal times_vector_rev: t_vector := (to_unsigned(4200000000 - 4000000000, 33),
                                          to_unsigned(4200000000 - 300000000, 33),
                                          to_unsigned(4200000000 - 4100000000, 33));

begin
    Divclk: process(clk, Reset)
    begin
        if Reset = '1' then
            DivAnods <= 0;
            clkAn <= '0';
        elsif rising_edge(clk) then
            DivAnods <= DivAnods + 1;
            if DivAnods = 100000 then
                DivAnods <= 0;
            elsif DivAnods > 49999 then
                clkAn <= '1';
            else
                clkAn <= '0';
            end if;
        end if;
    end process;

    process(clkAn, timer)
    begin
        -- Konwersja unsigned na integer dla wyświetlania
        time_10 <= to_integer((timer - diff) / 1000000000);
        time_1 <= to_integer(((timer - diff) / 100000000) mod 10);

        case time_10 is
            when 0 => Seven_Segment_10 <= "1000000"; -- 0
            when 1 => Seven_Segment_10 <= "1111001"; -- 1
            when 2 => Seven_Segment_10 <= "0100100"; -- 2
            when 3 => Seven_Segment_10 <= "0110000"; -- 3
            when 4 => Seven_Segment_10 <= "0011001"; -- 4
            when 5 => Seven_Segment_10 <= "0010010"; -- 5
            when 6 => Seven_Segment_10 <= "0000010"; -- 6
            when 7 => Seven_Segment_10 <= "1111000"; -- 7
            when 8 => Seven_Segment_10 <= "0000000"; -- 8
            when 9 => Seven_Segment_10 <= "0010000"; -- 9
            when others => Seven_Segment_10 <= "1000000"; -- null
        end case;

        case time_1 is
            when 0 => Seven_Segment_1 <= "1000000"; -- 0
            when 1 => Seven_Segment_1 <= "1111001"; -- 1
            when 2 => Seven_Segment_1 <= "0100100"; -- 2
            when 3 => Seven_Segment_1 <= "0110000"; -- 3
            when 4 => Seven_Segment_1 <= "0011001"; -- 4
            when 5 => Seven_Segment_1 <= "0010010"; -- 5
            when 6 => Seven_Segment_1 <= "0000010"; -- 6
            when 7 => Seven_Segment_1 <= "1111000"; -- 7
            when 8 => Seven_Segment_1 <= "0000000"; -- 8
            when 9 => Seven_Segment_1 <= "0010000"; -- 9
            when others => Seven_Segment_1 <= "1000000"; -- null
        end case;

        if clkAn = '1' then
            Cathodes <= Seven_Segment_1;
            AN0 <= "1110";
        else
            Cathodes <= Seven_Segment_10;
            AN0 <= "1101";
        end if;
    end process;

    process(clk, reset)
        variable temp_diff: unsigned(32 downto 0); -- Zmienna pomocnicza do obliczeń
    begin
        if reset = '1' then
            timer <= to_unsigned(4200000000, 33);
            state <= RED_STATE;
        elsif rising_edge(clk) then
            timer <= timer - 1;
            case state is
                when RED_STATE =>
                    red <= '1';
                    orange <= '0';
                    green <= '0';
                    temp_diff := to_unsigned(4200000000, 33) - times_vector(0) - times_vector(1);
                    diff <= temp_diff;
                    if timer = times_vector_rev(0) then
                        timer <= to_unsigned(4200000000, 33);
                        state <= ORANGE_STATE;
                    end if;
                when ORANGE_STATE =>
                    red <= '1';
                    orange <= '1';
                    green <= '0';
                    temp_diff := to_unsigned(4200000000, 33) - times_vector(1);
                    diff <= temp_diff;
                    if timer = times_vector_rev(1) then
                        timer <= to_unsigned(4200000000, 33);
                        state <= GREEN_STATE;
                    end if;
                when GREEN_STATE =>
                    red <= '0';
                    orange <= '0';
                    green <= '1';
                    temp_diff := to_unsigned(4200000000, 33) - times_vector(2);
                    diff <= temp_diff;
                    if timer = times_vector_rev(2) then
                        timer <= to_unsigned(4200000000, 33);
                        state <= RED_STATE;
                    end if;
            end case;
        end if;
    end process;
end Behaviour;