aha tot

// SRAM module for storing control code
module control_code_sram (
    input wire clk,
    input wire write_enable,
    input wire [2:0] data_in,    // Control code input
    output reg [2:0] data_out    // Stored control code
);
    reg [2:0] memory;

    always @(posedge clk) begin
        if (write_enable) begin
            memory <= data_in;
        end
        data_out <= memory;
    end
endmodule

// SRAM module for storing stop time
module stop_time_sram (
    input wire clk,
    input wire write_enable,
    input wire [3:0] hours_tens,
    input wire [3:0] hours_ones,
    input wire [2:0] mins_tens,
    input wire [3:0] mins_ones,
    input wire [3:0] secs_tens,
    input wire [3:0] secs_ones,
    output reg [23:0] stored_time    // Packed time format
);
    reg [23:0] memory;

    always @(posedge clk) begin
        if (write_enable) begin
            memory <= {hours_tens, hours_ones, mins_tens, mins_ones, secs_tens, secs_ones};
        end
        stored_time <= memory;
    end
endmodule

// Control module for clock operations
module clock_control(
    input wire [2:0] control_code,
    input wire reset_n,
    input wire clk,
    input wire [23:0] stored_stop_time,
    input wire [3:0] current_hours_tens,
    input wire [3:0] current_hours_ones,
    input wire [2:0] current_mins_tens,
    input wire [3:0] current_mins_ones,
    input wire [3:0] current_secs_tens,
    input wire [3:0] current_secs_ones,
    output reg clock_enable,
    output reg clear_time,
    output reg store_stop_time
);
    // Control codes
    parameter NO_CHANGE = 3'b000;
    parameter START     = 3'b001;
    parameter STOP      = 3'b010;
    parameter STOP_CLR  = 3'b011;

    // State register
    reg stopped_state;
    wire [23:0] current_time;

    assign current_time = {current_hours_tens, current_hours_ones,
                          current_mins_tens, current_mins_ones,
                          current_secs_tens, current_secs_ones};

    always @(posedge clk or negedge reset_n) begin
        if (!reset_n) begin
            clock_enable <= 0;
            clear_time <= 0;
            stopped_state <= 0;
            store_stop_time <= 0;
        end else begin
            store_stop_time <= 0; // Default value

            case (control_code)
                START: begin
                    clock_enable <= 1;
                    clear_time <= (stopped_state && control_code == STOP_CLR) ? 1 : 0;
                end
                STOP: begin
                    store_stop_time <= 1;
                    clock_enable <= 0;
                    stopped_state <= 0;
                end
                STOP_CLR: begin
                    clock_enable <= 0;
                    stopped_state <= 1;
                end
                default: begin // NO_CHANGE
                    clear_time <= 0;
                    if (current_time == stored_stop_time && control_code == STOP) begin
                        clock_enable <= 0;
                    end
                end
            endcase
        end
    end
endmodule

// Clock divider module
module clock_divider #(
    parameter CLK_HZ = 50000000
)(
    input  wire clk_in,
    input  wire reset_n,
    input  wire enable,
    output reg  sec_pulse
);
    parameter CYCLES_PER_10ms = 50_000/2;
    parameter TICKS_PER_SEC = 1000;

    reg [15:0] cycleCnt = 0;
    reg [9:0] timeCnt = 0;

    always @(posedge clk_in or negedge reset_n) begin
        if (!reset_n) begin
            cycleCnt <= 0;
            timeCnt <= 0;
            sec_pulse <= 0;
        end else if (enable) begin
            if (cycleCnt == CYCLES_PER_10ms - 1) begin
                cycleCnt <= 0;
                timeCnt <= timeCnt + 1;
                if (timeCnt == TICKS_PER_SEC - 1) begin
                    timeCnt <= 0;
                    sec_pulse <= ~sec_pulse;
                end
            end else begin
                cycleCnt <= cycleCnt + 1;
            end
        end
    end
endmodule

// Seconds counter module
module seconds_counter(
    input  wire       clk,
    input  wire       reset_n,
    input  wire       sec_pulse,
    input  wire       clear,
    output reg [3:0]  ones,
    output reg [3:0]  tens,
    output reg        min_pulse
);
    always @(posedge clk or negedge reset_n) begin
        if (!reset_n || clear) begin
            ones <= 0;
            tens <= 0;
            min_pulse <= 0;
        end else if (sec_pulse) begin
            min_pulse <= 0;
            if (ones < 9) begin
                ones <= ones + 1;
            end else begin
                ones <= 0;
                if (tens < 5) begin
                    tens <= tens + 1;
                end else begin
                    tens <= 0;
                    min_pulse <= 1;
                end
            end
        end
    end
endmodule

// Minutes counter module
module minutes_counter(
    input  wire       clk,
    input  wire       reset_n,
    input  wire       min_pulse,
    input  wire       clear,
    output reg [3:0]  ones,
    output reg [2:0]  tens,
    output reg        hour_pulse
);
    always @(posedge clk or negedge reset_n) begin
        if (!reset_n || clear) begin
            ones <= 0;
            tens <= 0;
            hour_pulse <= 0;
        end else if (min_pulse) begin
            hour_pulse <= 0;
            if (ones < 9) begin
                ones <= ones + 1;
            end else begin
                ones <= 0;
                if (tens < 5) begin
                    tens <= tens + 1;
                end else begin
                    tens <= 0;
                    hour_pulse <= 1;
                end
            end
        end
    end
endmodule

// Hours counter module (modified for 99 hours)
module hours_counter(
    input  wire       clk,
    input  wire       reset_n,
    input  wire       hour_pulse,
    input  wire       clear,
    output reg [3:0]  ones,
    output reg [3:0]  tens
);
    always @(posedge clk or negedge reset_n) begin
        if (!reset_n || clear) begin
            ones <= 0;
            tens <= 0;
        end else if (hour_pulse) begin
            if (tens == 9 && ones == 9) begin  // Reset at 99:59:59
                tens <= 0;
                ones <= 0;
            end else if (ones < 9) begin
                ones <= ones + 1;
            end else begin
                ones <= 0;
                tens <= tens + 1;
            end
        end
    end
endmodule

// Seven segment decoder module
module seven_segment_decoder(
    input  wire [3:0] digit,
    output reg  [6:0] segments
);
    always @(*) begin
        case(digit)
            4'h0: segments = 7'b1000000;
            4'h1: segments = 7'b1111001;
            4'h2: segments = 7'b0100100;
            4'h3: segments = 7'b0110000;
            4'h4: segments = 7'b0011001;
            4'h5: segments = 7'b0010010;
            4'h6: segments = 7'b0000010;
            4'h7: segments = 7'b1111000;
            4'h8: segments = 7'b0000000;
            4'h9: segments = 7'b0010000;
            default: segments = 7'b1111111;
        endcase
    end
endmodule

// Top module
module clock_with_display #(
    parameter CLK_HZ = 50000000
)(
    input  wire       clk_in,
    input  wire       reset_n,
    input  wire [2:0] control_code,
    input  wire       control_code_write_enable,  // New input for control code SRAM
    output wire [6:0] HEX0,    // Seconds ones
    output wire [6:0] HEX1,    // Seconds tens
    output wire [6:0] HEX2,    // Minutes ones
    output wire [6:0] HEX3,    // Minutes tens
    output wire [6:0] HEX4,    // Hours ones
    output wire [6:0] HEX5     // Hours tens
);
    // Internal signals
    wire sec_pulse, min_pulse, hour_pulse;
    wire [3:0] sec_ones, sec_tens;
    wire [3:0] min_ones;
    wire [2:0] min_tens;
    wire [3:0] hour_ones;
    wire [3:0] hour_tens;
    wire clock_enable, clear_time;
    wire store_stop_time;
    wire [2:0] stored_control_code;
    wire [23:0] stored_stop_time;

    // Control code SRAM instance
    control_code_sram control_mem (
        .clk(clk_in),
        .write_enable(control_code_write_enable),
        .data_in(control_code),
        .data_out(stored_control_code)
    );

    // Stop time SRAM instance
    stop_time_sram stop_time_mem (
        .clk(clk_in),
        .write_enable(store_stop_time),
        .hours_tens(hour_tens),
        .hours_ones(hour_ones),
        .mins_tens(min_tens),
        .mins_ones(min_ones),
        .secs_tens(sec_tens),
        .secs_ones(sec_ones),
        .stored_time(stored_stop_time)
    );

    // Clock control instance
    clock_control ctrl (
        .clk(clk_in),
        .reset_n(reset_n),
        .control_code(stored_control_code),
        .stored_stop_time(stored_stop_time),
        .current_hours_tens(hour_tens),
        .current_hours_ones(hour_ones),
        .current_mins_tens(min_tens),
        .current_mins_ones(min_ones),
        .current_secs_tens(sec_tens),
        .current_secs_ones(sec_ones),
        .clock_enable(clock_enable),
        .clear_time(clear_time),
        .store_stop_time(store_stop_time)
    );

    // Clock divider instance
    clock_divider #(
        .CLK_HZ(CLK_HZ)
    ) clk_div (
        .clk_in(clk_in),
        .reset_n(reset_n),
        .enable(clock_enable),
        .sec_pulse(sec_pulse)
    );

    // Seconds counter instance
    seconds_counter sec_cnt (
        .clk(clk_in),
        .reset_n(reset_n),
        .sec_pulse(sec_pulse),
        .clear(clear_time),
        .ones(sec_ones),
        .tens(sec_tens),
        .min_pulse(min_pulse)
    );

    // Minutes counter instance
    minutes_counter min_cnt (
        .clk(clk_in),
        .reset_n(reset_n),
        .min_pulse(min_pulse),
        .clear(clear_time),
        .ones(min_ones),
        .tens(min_tens),
        .hour_pulse(hour_pulse)
    );

    // Hours counter instance
    hours_counter hour_cnt (
        .clk(clk_in),
        .reset_n(reset_n),
        .hour_pulse(hour_pulse),
        .clear(clear_time),
        .ones(hour_ones),
        .tens(hour_tens)
    );

    // Seven segment decoder instances
    seven_segment_decoder seg0 (.digit(sec_ones),  .segments(HEX0));
    seven_segment_decoder seg1 (.digit(sec_tens),  .segments(HEX1));
    seven_segment_decoder seg2 (.digit(min_ones),  .segments(HEX2));
    seven_segment_decoder seg3 (.digit({1'b0, min_tens}), .segments(HEX3));
    seven_segment_decoder seg4 (.digit(hour_ones), .segments(HEX4));
    seven_segment_decoder seg5 (.digit(hour_tens), .segments(HEX5));

endmodule