module module_name (<ports declaration>);
…
// stage 0 next-state logic
<next-state register signals declaration>
always @*
    begin
    st0_reg_next = in0 + in1;
    …
    end

// stage 0 register assignment logic
<register signals declaration >
always @(posedge clk_i)
    begin
    if (rst_i) begin st0_reg <= 0; … end;     // clearing state on reset
    else begin st0_reg <= st0_reg_next; … end;    // registering next_state
    end

// other stages
…

endmodule