fsm4

`timescale 1ns / 1ps

module fsm4(
    input clk,
    input reset,
    input enable,
    input [31:0] A,
    input [31:0] B,
    output reg [35:0] res
);

parameter PLUG = 0;
parameter SUM_A_B = 1;
parameter SUM1_MUL_4 = 2;
parameter SUM_LMUL_B = 3;
parameter B_DIV_2 = 4;
parameter A_MUL_4 = 5;
parameter SUM_BDIV_AMUL = 6;
parameter L_BRACKETS_DIV_2 = 7;
parameter END_SUM = 8;

reg [3:0] cur_state = 0;
reg [3:0] next_state = 0;
reg [35:0] sum_1, sum_2, mul_1, div_1;

always @(posedge clk or posedge reset or negedge reset) begin
    if (reset) begin
        res <= 0;
        cur_state = PLUG;
    end
    if (enable) begin
        res <= 0;
    end
end

always @(negedge clk) begin
    case (cur_state)
        PLUG:
            cur_state = SUM_A_B;
        SUM_A_B:
            cur_state = SUM1_MUL_4;
        SUM1_MUL_4:
            cur_state = SUM_LMUL_B;
        SUM_LMUL_B:
            cur_state = B_DIV_2;
        B_DIV_2:
            cur_state = A_MUL_4;
        A_MUL_4:
            cur_state = SUM_BDIV_AMUL;
        SUM_BDIV_AMUL:
            cur_state = L_BRACKETS_DIV_2;
        L_BRACKETS_DIV_2:
            cur_state = END_SUM;
        END_SUM:
            cur_state = 0;
        default:
            cur_state = 0;
    endcase
end

always @(posedge clk) begin
    case (cur_state)
        PLUG: ;
        SUM_A_B:
            sum_1 <= A + B;
        SUM1_MUL_4:
            mul_1 <= sum_1 << 2;
        SUM_LMUL_B:
            sum_1 <= mul_1 + B;
        B_DIV_2:
            div_1 <= B >> 1;
        A_MUL_4:
            mul_1 <= A << 2;
        SUM_BDIV_AMUL:
            sum_2 <= div_1 + mul_1;
        L_BRACKETS_DIV_2:
            div_1 <= sum_1 >> 1;
        END_SUM:
            res <= div_1 + sum_2;
        default:
            next_state = 0;
    endcase
end

endmodule